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sep, 2011 v0.21p F71889A F71889A super hardware monitor + lpc i/o release date: sep, 2011 version: v0.21p
sep, 2011 v0.21p F71889A F71889A datasheet revision history please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales. version date page revision history v0.10p 2010/4 - preliminary version. v0.11p ~ v0.19p 2010/5 ~ 2011/6 - shorten history description v0.20p 2011/7/18 72-73 add usben/vccgate timing and susc# timing protection mode configuration register ? index 02h, bit 3 v0.21p 2011/9/14 made correction & clarification update vin3 (pin96) description
sep, 2011 v0.21p F71889A table of content 1. general de scripti on ........................................................................................................ 1 2. featur e list ............................................................................................................... ...... 1 3. key spec ification .......................................................................................................... .. 4 4. block diagram .............................................................................................................. .. 5 5. pin conf igurat ion .......................................................................................................... .. 6 6. pin de scription ............................................................................................................ ... 7 6.1 powe r pin ................................................................................................................. ... 7 6.2 lpc in terface ............................................................................................................. . 8 6.3 uart, gpio and 80-port ............................................................................................ 8 6.4 parallel port ............................................................................................................. . 10 6.5 hardware monitor, sir, cir, erp ............................................................................ 11 6.6 kbc f unction ............................................................................................................ 1 3 6.7 cir, gpio, other s function ..................................................................................... 13 6.8 acpi functi on pins ................................................................................................... 14 7. function de scription ..................................................................................................... 1 6 7.1. power on str apping opti on ....................................................................................... 16 7.2. hardware monitor ...................................................................................................... 16 7.3. hardware moni tor regist er ....................................................................................... 30 7.4. keyboard c ontroller .................................................................................................. 63 7.5. 80 port .................................................................................................................. .... 65 7.6. acpi function ........................................................................................................... 65 7.7. peci f unction ........................................................................................................... 71 7.8. sst function ............................................................................................................ 72 7.9. tsi f unction ............................................................................................................. . 72 7.10. power saving function ......................................................................................... 72 7.11. cir f unction ......................................................................................................... 74 7.12. scan code f unction ............................................................................................. 75 8 register de scription ..................................................................................................... 76 8.1 global control register s ........................................................................................... 80 8.2 uart1 register s (cr01) .......................................................................................... 85 8.3 uart 2 regist ers (cr02) ......................................................................................... 86 8.4 parallel port r egisters (cr 03) .................................................................................. 87 8.5 hardware monitor r egisters (cr 04) ......................................................................... 88 8.6 kbc register s (cr05) .............................................................................................. 88
sep, 2011 v0.21p F71889A 8.7 gpio registers (cr06) (all register s of gpio are power ed by vsb3v) .................. 89 8.8 watch dog timer r egisters (cr 07) ........................................................................ 104 8.9 cir register s (cr08) ............................................................................................. 105 8.10 pme, acpi and erp r egisters (cr0 a) .................................................................. 106 8.11 vref control r egisters (cr0 b) ............................................................................. 114 9 electrical char acteristics ............................................................................................ 115 10 ordering info rmation ................................................................................................... 118 11 top marking s pecification ........................................................................................... 118 12 package dimens ions .................................................................................................. 119 13 applicatio n circuit ....................................................................................................... 120
sep, 2011 v0.21p -1- F71889A 1. general description the F71889A which is the featured io chip for new generational pc system is equipped with one ieee 1284 parallel port, two uart ports, kbc, 80-port (multi with com2), cir with rc6 and smk qp protocols supported and 54 gpio pins. the F71889A integrated with hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate dual current type temp. measurement for cpu thermal diode or external transistors 2n3906. the F71889A provides flexible features for multi-directional application. for instance, irq sharing function also designed in uart feature for particular usage and accurate current mode h/w monitor will be worth in measurement of temperature, provides 3 modes fan speed control mechanism included manual mode/speed mode/temperature mode for users? selection. additionally, integrated 80-port, and 5vdual voltage switch and adjustable voltage reference outputs related functions. the 80-port is for engineering and debuging usage. F71889A also provides 5v dual controller and some voltage reference outputs for system application. others, the F71889A supports newest amd new interface tsi and intel peci 3.0 /sst interfaces and intel ibx peak smbus for temperature reading. these features will help you more and improve product value. in order to save the current consumption when the system is in the soft off state which is so called power saving function. the power saving function supports the system boot-on not only by pressing the power button but also by the wake-up events (gpio5x, cir, ri#) . when the system enters the s3/s4/s5 state, F71889A can cut off the vsb power rail which supplies power source to the devices like the lan chip, the chipset, the sio, the audio codec, dram, and etc. the pc system can be simulated to g3 -like state when the system enters s3/s4/s5 states. at the g3-like state, the F71889A consumes 5vsb power rail only. the integrated two control pins are utilized to turn on or off vsb power rail in the g3-like status. the turned on vsb rail is supplied to a wake up device to fulfill a low power consumption system which supports a wake up function. finally, the F71889A is powered by 3.3v voltage, with the lpc interface in the package of 128-lqfp (14mm*14mm) green package. 2. feature list general functions 9 comply with lpc spec. 1.1 9 support dpm (device power management), acpi 9 provides two uarts, kbc and parallel port
sep, 2011 v0.21p -2- F71889A 9 h/w monitor functions 9 support ovp & uvp for vcc and vin 5/6 9 reference voltage outputs support 9 5vdual voltage switch 9 support amd tsi interface and intel sst interface 9 support peci spec.3.0 9 support cir with rc6 and smk qp protocols 9 support ibx protocol smbus interface 9 80-port interface from com2 9 support led blinking function at deep s5 9 54 gpio pins for flexible application 9 provide power saving funtion (comply erp lot 6.0) 9 support intel cougar point timing sequence 9 24/48 mhz clock input 9 packaged in 128-lqfp green package and powered by 3.3vcc uart 9 two high-speed 16c550 compatible uart with 16-byte fifos 9 fully programmable serial-interface characteristics 9 baud rate up to 115.2k 9 support irq sharing 80-port interface 9 monitor 0x80 port and output the value via signals defined for 7-segment display. 9 high nibble and low nibble are outputted interleaved at 1khz frequency. 9 80-port output by com2 interface. parallel port 9 one ps/2 compatible bi-directional parallel port 9 support enhanced parallel port (epp) ? compatible with ieee 1284 specification 9 support extended capabilities port (ecp) ? compatible with ieee 1284 specification 9 enhanced printer port back-drive current protection hardware monitor functions 9 3 dual current type ( 3 ) thermal inputs for cpu thermal diode and 2n3906 transistors 9 temperature range -40 ~127 9 9 sets voltage monitoring (6 external and 3 internal powers) 9 high limit signal (pme#) for vcore level
sep, 2011 v0.21p -3- F71889A 9 3 fan speed monitoring inputs 9 3 fan speed pwm/dc control outputs(support 3 wire and 4 wire fans) 9 issue pme# and ovt# hardware signals output 9 case intrusion detection circuit 9 watchdog# comparison of all monitored values keyboard controller 9 compatibility with the 8042 9 support ps/2 mouse 9 support both interrupt and polling modes 9 hardware gate a20 and hardware keyboard reset gpio 9 gpio 53 and gpio 54 can control the duty of pwm pin 9 54 gpio pins for flexible application system volume control 9 gpio 50, gpio 51 and gpio 52 can control the system volume & mute function by lpc interface 9 windows osd can detect the system volu me control input without any driver installation. infrared 9 support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps cir 9 support microsoft windows vista / windows 7 ir receiver 9 support rc6 and quatro pulse protocols 9 support learning function 9 provide data receiver led 9 2 ir receiver with long range frequency and another with wideband application integrate amd tsi interface integrate intel sst interface support intel cougar point timing (dsw) support peci 3.0 support ibx protocol smbus interface
sep, 2011 v0.21p -4- F71889A 5v dual voltage switch 9 provide acpi-compliant 5vdual voltage switch 9 5vdual for usb/keyboard/mouse application adjustable voltage reference outputs 9 enable pin for vref2 and 3 voltage reference output control 9 0.9v default output on vref1~3 pins 9 adjustable voltage range from 0~2.295v power saving function 9 g3-like timing control 9 comply with erp lot 6.0 9 three control pins for vsb power sources control 9 two event input pins for wakeup devices package 9 128-pin lqfp (14mm * 14mm) green package noted: patented tw207103 tw207104 tw220442 us6788131 b1 twi235231 tw237183 twi263778 3. key specification supply voltage 3.0v to 3.6v operating supply current 10ma typ.
sep, 2011 v0.21p -5- F71889A 4. block diagram cpu chipset (nb+sb) usb ide power savin g irda parallel com led ( gpio ) tem p erature v olta g e fan super h/w monitor + i/o F71889A acpi ibx bus interface ac?97 kbc 80-port a mdtsi peci sst 5v dual controller
sep, 2011 v0.21p -6- F71889A 5. pin configuration figure1. F71889A pin configuration
sep, 2011 v0.21p -7- F71889A 6. pin description i/o 16t - ttl level bi-directional pin with 16 ma source-sink cap ability. i/ood 12t i/ood 18t i/ood 12st,lv i/ood 12st,5v i/od 16st,5v - ttl level bi-directional pin, can select to od or out by register, with 12 ma source-sink capability. ttl level bi-directional pin, can select to od or out by register, with 18 ma source-sink capability. - low level bi-directional pin with schmitt tri gger, can select to od or out by register, with 12 ma source-sink capability. - ttl bi-directional pin with schmitt trigger, can select to od or out by register, with 12 ma source-sink capab ility, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 16 ma sink capability, 5v tolerance. od 16,u10,5v i/o 12st,5v i/o d8,st,lv i/o s1,d8st,lv i/od 12st,lv o 8 , u47 , 5v - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, output with 12 ma sink capability, 5v tolerance. - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.) with schmitt trigger. output with 8ma drive - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.) with schmitt trigger. output with 8ma drive and 1ma sink capability. - low level bi-directional pin with schmitt trigger. open-drain output with 12ma sink capability. - open-drain pin with 8 ma source-sink capabilit y, pull-up 47k ohms, 5v tolerance. o 12 o 16 o 18 o 30 - output pin with 12 ma source-sink capability. - output pin with 16 ma source-sink capability. - output pin with 18 ma source-sink capability. - output pin with 30 ma source-sink capability. aout - output pin(analog). od 12 od 12,5v o 24 i/od 14t - open-drain output pin with 12 ma sink capability. - open-drain output pin with 12 ma sink capability, 5v tolerance. - output pin with 24 ma sink capability. - ttl level bi-directional pin, open-drain output with 14 ma sink capability. in t,5v in st - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. in st , 5v - ttl level input pin and schmitt trigger, 5v tolerance. in st , lv - ttl low level input pin (vih ? 0.9v, vil ? 0.6v.) ain - input pin(analog). p - power. 6.1 power pin pin no. pin name type description 1,35 3vcc p 3.3v power supply input which supports ovp & uvp. 49 vsb5v (v5a) p 5v stan dby power supply input. 65 i_vsb3v p 3.3v internal stan dby power regulates from vsb5v 82 vbat p 3.3v battery input 88 agnd(d-) p analog gnd 20, 50, 70, 117 gnd p digital gnd 99 3vsb p voltage input for 3.3v vsb.
sep, 2011 v0.21p -8- F71889A 6.2 lpc interface pin no. pin name type pwr description 27 lreset# in st,5v 3vcc reset signal. it can connect to pcirst# signal on the host. 28 ldrq# o 16 3vcc encoded dma request signal. 29 serirq i/o 16t 3vcc serial irq input/output. 30 lframe# in st 3vcc indicates start of a new cycle or termination of a broken cycle. 31-34 lad[0:3] i/o 16t 3vcc these signal lines communic ate address, control, and data information over the lpc bus between a host and a peripheral. 36 pciclk in st 3vcc 33mhz pci clock input. 37 clkin in st 3vcc system clock input. according to the input frequency 24/48mhz. 6.3 uart, gpio and 80-port pin no. pin name type pwr description 7 gpio40 od 16t i_vsb3v general purpose io. (select by register) cir_led# od 12, 5v led for cir to indicate receiver is receiving data. 8 gpio41 od 16t i_vsb3v general purpose io. (select by register) 9 gpio42 od 16t i_vsb3v general purpose io. (select by register) 10 gpio43 od 16t i_vsb3v general purpose io. (select by register) 11 gpio44 od 16t i_vsb3v general purpose io. (select by register) 12 gpio45 od 16t i_vsb3v general purpose io. (select by register) 13 gpio46 od 16t i_vsb3v general purpose io. (select by register) 14 gpio47 od 16t i_vsb3v general purpose io. (select by register) 15 gpio50 od 16t i_vsb3v general purpose io. could be selected to volume up function via scan code register. 16 gpio51 od 16t i_vsb3v general purpose io. could be selected to volume down function via scan code register. 17 gpio52 od 16t i_vsb3v general purpose io. could be selected to mute function via scan code. 18 gpio53 od 16t i_vsb3v general purpose io. could be selected to pwm up function via register. 19 gpio54 od 16t i_vsb3v general purpose io. could be selected to pwm down function vis register. 118 dcd1# in t,5v 3vcc data carrier detect. an ac tive low signal indicates the modem or data set has detected a data carrier. 119 ri1# in t,5v 3vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 120 cts1# in t,5v 3vcc clear to send is the modem control input. 121 dtr1# o 8,u47,5v 3vcc uart 1 data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. internal 47k ohms pulled high and disable after power on strapping.
sep, 2011 v0.21p -9- F71889A fan60_100 in t,5v power on strapping pin: 1(default): (internal pull high) power on fan speed default duty is 60%.(pwm) 0: (external pull down) power on fan speed default duty is 100%.(pwm ) 122 rts1# o 8,u47,5v 3vcc uart 1 request to send. an active low signal informs the modem or data set that the controller is ready to send data. internal 47k ohms pulled high and disable after power on strapping. 80port_trap in t,5v power on strapping pin: 1(default) : default 80-port enable (internal pull high) 80 port decode output from com2 interface 0 : disable 80-port function 123 dsr1# in t,5v 3vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. 124 sout1 o 8,u47,5v 3vcc uart 1 serial output. used to transmit serial data out to the communication link. internal 47k ohms pulled high and disable after power on strapping. config4e_2e in t,5v power on strapping: (internal pull high) 1(default): configuration register ? 4e 0 : configuration register ? 2e 125 sin1 in t,5v 3vcc serial input. used to receive serial data through the communication link. 126 dcd2# in t,5v 3vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. segg o 18 segg for 7-segment display. (select by pin 122 power on strapping) gpio30 i/ood 18t general purpose io. (select by register) 127 ri2# in t,5v 3vcc ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. segf o 18 segf for 7-segment display. (select by pin 122 power on strapping) gpio31 i/ood 18t general purpose io. (select by register) 128 cts2# in t , 5v 3vcc clear to send is the modem control input. sega o 18 sega for 7-segment display. (select by pin 122 power on strapping) gpio32 i/ood 18t general purpose io. (select by register) 2 dtr2# o 8,u47,5v 3vcc uart 2 data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. internal 47k ohms pulled high and disable after power on strapping. segd o 18 segd for 7-segment display. (select by pin 122 power on strapping) gpio33 i/ood 18t general purpose io. (select by register) 3 rts2# o 8,u47,5v 3vcc uart 2 request to send. an active low signal informs the modem or data set that the controller is ready to send data. internal 47k ohms pulled high and disable after power on strapping. segc o 18 segc for 7-segment display. (select by pin 122 power on strapping) gpio34 i/ood 18t general purpose io. (select by register)
sep, 2011 v0.21p -10- F71889A pwm_dc in t,5v power on strapping : 1 (default): fan control method will be in pwm mode 0 drive :fan control method will be in linear mode 4 dsr2# in t,5v 3vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. l# o 30 l# for 7-segment display. (select by pin 122 power on strapping) gpio35 i/ood 12t general purpose io. (select by register) 5 sout2 o 8,u47,5v 3vcc uart 2 serial output. used to transmit serial data out to the communication link. internal 47k ohms pulled high and disable after power on strapping. segb o 18 segb for 7-segment display. (select by pin 122 power on strapping) gpio36 i/ood 18t general purpose io. (select by register) ovp_strap in t,5v power on strapping pin for ovp/uvp protection function. 1: default is disabled alarm mode. voltage protection function is enabled via setting the related register. 0: force mode which is always enabled after power on. 6 sin2 in t,5v 3vcc serial input. used to receive serial data through the communication link. sege o 18 sege for 7-segment display. (select by pin 122 power on strapping) gpio37 i/ood 18t general purpose io. (select by register) 6.4 parallel port pin no. pin name type pwr description 100 slct in st,5v 3vcc an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. gpio60 i/ood 12t general purpose io. 101 pe inst,5v 3vcc an active high input on this pin indicates that the printer has detected the end of the paper. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio61 i/ood 12t general purpose io. 102 busy in st,5v 3vcc an active high input indicates that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. gpio62 i/ood 12t general purpose io. 103 ack# in st,5v 3vcc an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio63 i/ood 12t general purpose io. 104 slin# i/ood 12,5v 3vcc output line for detection of printer selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode.
sep, 2011 v0.21p -11- F71889A 105 init# i/ood 12,5v 3vcc output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio64 i/ood 12t general purpose io. 106 err# in st,5v 3vcc an active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio65 i/ood 12t general purpose io. 107 afd# i/ood 12,5v 3vcc an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio66 i/ood 12t general purpose io. 108 stb# i/ood 12,5v 3vcc an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio67 i/ood 12t general purpose io. 109 pd0 i/o 12st,5v 3vcc parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. gpio70 i/ood 12t general purpose io. 110 pd1 i/o 12st,5v 3vcc parallel port data bus bit 1. gpio71 i/ood 12t general purpose io. 111 pd2 i/o 12st , 5v 3vcc parallel port data bus bit 2. gpio72 i/ood 12t general purpose io. 112 pd3 i/o 12st,5v 3vcc parallel port data bus bit 3. gpio73 i/ood 12t general purpose io. 113 pd4 i/o 12st , 5v 3vcc parallel port data bus bit 4. gpio74 i/ood 12t general purpose io. 114 pd5 i/o 12st,5v 3vcc parallel port data bus bit 5. gpio75 i/ood 12t general purpose io. 115 pd6 i/o 12st , 5v 3vcc parallel port data bus bit 6. gpio76 i/ood 12t general purpose io. 116 pd7 i/o 12st , 5v 3vcc parallel port data bus bit 7. gpio77 i/ood 12t general purpose io. 6.5 hardware monitor, sir, cir, erp pin no. pin name type pwr description 93-94 vin6~vin5 ain i_vsb3v voltage input 6 ~ 5. support ovp & uvp function, and default is disable. 95-97 vin4~vin2 ain i_vsb3v voltage input 4 ~ 2. *please connect vin3 (pin96) to 5vcc if usben/vccgate were used.(be careful of the voltage input range 0~2.048) * if vin3 is not used, pull high (4.7k) to 3vcc . 98 vcore(vin1) ain i_vsb3v voltage input for vcore. 21 fanin1 in st,5v 3vcc fan 1 tachometer input. 22 fanctl1 od 12,5v aout 3vcc fan 1 control output. this pin provides pwm duty-cycle output or a voltage output.
sep, 2011 v0.21p -12- F71889A 23 fanin2 in st,5,4v 3vcc fan 2 tachometer input. 24 fanctl2 od 12,5v aout 3vcc fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. 25 fanin3 in st , 5v 3vcc fan 3 speed input. gpio10 i/ood 12t general purpose io. (select by register) irrx1 in st infrared receiver input. (select by register) 26 fanctl3 od 12,5v aout 3vcc fan 3 control output. the pwm output frequency can be programmed to 220hz for lcd backlight control. gpio11 i/ood 12t general purpose io. (select by register) irtx1 o 12 infrared transmitter outp ut. (select by register) 89 d3+(system) ain i_vsb3v thermal diode/transistor temperature sensor input for system use. 90 d2+ ain i_vsb3v thermal diode/transistor temperature sensor input. 91 d1+(cpu) ain i_vsb3v cpu thermal diode/transistor temperature sensor input. this pin is for cpu use. 92 vref aout i_vsb3v voltage sensor output. 75 pme# od 12,5v i_vsb3v generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from the s3 state. 45 event_in0# in st,5v i_vsb3v wake-up event input. the signal input wakes the system up from the sleep state. 46 usben o 12 i_vsb3v usb power control signal. **if usben was used, please connect pin96 to 5vcc (be careful of the voltage input range 0~2.048v.) event_in1# in st,5v wake-up event input. the signal input wakes the system up from the sleep state. 47 erp_ctrl0# od 12 i_vsb3v standby power rail control pin 0. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. 48 erp_ctrl1# od 12 i_vsb3v standby power rail control pin 1. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. 61 ovt# od 12,5v i_vsb3v over temperature signal output. 40 cir_led# od 12 , 5v 3vcc led for cir to indicate receiver is receiving data. gpio12 i/ood 12t general purpose io. wdtrst# od 12,5v watch dog timer signal output. (selecty by register) 41 cirtx o 20 3vcc cir transmitter to transmit data. tsi_clk i/od 12st,lv clock output for amd tsi interface. (select by register) ibx_clk i/od 12st,lv clock output for intel pch (ibx peak) interface. (select by register) gpio13 i/ood 12t general purpose io. (selecty by register)
sep, 2011 v0.21p -13- F71889A 42 cirwb# in st , 5v 3vcc cir wide-band receiver input for learning function. tsi_dat i/od 12st , lv amd tsi data interface. (select by register) ibx_sda i/od 12st,lv intel pch (ibx peak) data interface pin. (select by register) gpio14 i/ood 12t general purpose io. (selecty by register) 43 sst i/o d8 , st , lv 3vcc intel sst hardware monitor interface. (default) tsi_clk i/od 12st,lv clock output for amd tsi interface. (select by register) ibx_clk i/od 12st,lv clock output for intel pch (ibx peak) interface. (select by register) gpio15 i/ood 12st,lv general purpose io. (selecty by register) 44 peci i/o s1,d8st,lv 3vcc intel peci hardware monitor interface. (default) tsi_dat i/od 12st,lv amd tsi data interface. (select by register) ibx_sda i/od 12st,lv intel pch (ibx peak) data interface pin. (select by register) gpio16 i/ood 12st,lv general purpose io. (selecty by register) 6.6 kbc function pin no. pin name type pwr description 38 kbrst# od 16,u10,5v 3vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p20) 39 ga20 od 16,u10,5v 3vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p21) 66 kdata i/od 16st,5v i_vsb3v keyboard data. 67 kclk i/od 16st,5v i_vsb3v keyboard clock. 68 mdat i/od 16st,5v i_vsb3v ps2 mouse data. 69 mclk i/od 16st,5v i_vsb3v ps2 mouse clock. 6.7 cir, gpio, others function pin no. pin name type pwr description 51 cirrx# in st , 5v i_vsb3v cir long-range receiver input gpio25 i/ood 12st,lv general purpose pin. 52 slp_sus# in st,lv i_vsb3v this pin asserts low which comes from pch to shut off suspend power rails externally to enhance power saving function. gpio26 i/ood 12st,lv general purpose pin. 53 sus_warn# in st,lv i_vsb3v this pin asserts low when the pch is planning to enter the dsw power state. it can detect 5vdual level with delay setting supported.the delay time is 1ms~8s (default 4s) gpio27 i/ood 12st,lv general purpose pin. 54 erp_ctrl2# od 12 i_vsb3v standby power rail control pin 2. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail.
sep, 2011 v0.21p -14- F71889A gpio00 i/ood 12st,lv general purpose pin. 55 sus_ack# ood 16,5v i_vsb3v this pin must wait suswarn# signal for entering dsw power state. gpio01 i/ood 12t general purpose pin. 56 dpwrok od 12,5v vbat resume reset# function, it is power good signal of 5vsb which is delayed 66ms as 5vsb arrives at 4.4v. couple this pin to pch when system supports intel dsw state function. gpio02 i/od 12t i_vsb3v general purpose pin. 57 slotocc# in st,5v i_vsb3v cpu slotocc# input. gpio03 i/ood 12t general purpose pin. 58 gpio04 i/ood 12t i_vsb3v general purpose pin. led_vsb ood 12 power led for vsb 59 gpio05 i/ood 12t i_vsb3v general purpose pin. led_vcc ood 12 power led for vcc 60 susc# o 12 i_vsb3v s5 latch signal. gpio06 i/ood 12t general purpose pin. beep od 12 beep pin. alert# od 12 alert a signal when something issues. 6.8 acpi function pins pin no. pin name type pwr description 62 pcirst1# od 12,5v i_vsb3v it is an output buffer of lreset#. 63 pcirst2# o 24 i_vsb3v it is an output buffer of lreset#. 64 pcirst3# o 24 i_vsb3v it is an output buffer of lreset#. 71 vccgate o 12 i_vsb3v driver output for 5vcc. connec t this pin to the gate of a suitable nmos. **if vccgate was used, please connect pin96 to 5vcc (be careful of voltage input range 0~2.048v). 72 dualgate od 12 i_vsb3v driver output for 5vsb. connec t this pin to the gate of a suitable pmos.. 73 s5# in st,5v i_vsb3v s5# input. this pin companies with s3# to indicate operating state from s0 to s3 and s4/s5 sleep states. 74 atxpg_in in st,5v i_vsb3v atx power good input. 76 psin# in st,5v i_vsb3v main power switch button input. 77 psout# od 12,5v i_vsb3v panel switch output. this pin is low active and pulse output. it is power on request output. 78 s3# in st,5v i_vsb3v s3# input: main power on-off switch input. 79 pson# od 12,5v i_vsb3v power supply on-off control output. connect to atx power supply ps_on# signal. 80 pwok od 12,5v vbat pwrok function, it is power good signal of vcc, which is delayed 100ms (default) as vcc arrives at 2.8v. it falls when s3# gets low. 81 rsmrst# od 12,5v vbat resume reset# function, it is power good signal of 5vsb and 3vsb, which is delayed 66ms as 3vsb arrives at 2.95v. there is an option to set rsmrst#
sep, 2011 v0.21p -15- F71889A falls when 3vsb drops to 2.3v. 83 copen# in st,5v vbat case open detection #. this pin is connected to a specially designed low power cmos flip-flop back by the battery for case open state preservation during power loss. 84 vref_en in st,5v i_vsb3v reference voltage dac output enable pin. input high to this pin to enable vref2 and vref3. on the contrary, vref2 and vref3 will be disabled when input low to this pin. 85 vref3 aout i_vsb3v deafault 0.9v reference voltage output. the on/off sequence of this pin can be controlled by s3#, s5#, and vref_en. 86 vref2 aout i_vsb3v deafault 0.9v reference voltage output. the on/off sequence of this pin can be controlled by s3#, s5#, and vref_en. 87 vref1 aout i_vsb3v deafault 0.9v reference voltage output. deafault 0.9v reference voltage output. the on/off sequence of this pin can be controlled by s3# and s5#.
sep, 2011 v0.21p -16- F71889A 7. function description 7.1. power on strapping option the F71889A provides five pins for power on har dware strapping to select functions. power on strapping value follows ttl voltage level. below t able describes how to set the functions you want. table1. power on trap configuration pin no. symbol v alue description 3 pwm_dc 1 fan control mode: pwm mode. ( default) 0 fan control mode: dac mode. 5 ovp_strap 1 default is disabled alarm mode. voltage protection function is enabled via setting the related register. 0 force mode which is always enabled after power on. 121 fan60_100 1 fan full duty is 60%.(default) 0 fan full duty is 100%. 122 80port_trap 1 enable the 80 port function. (default) 0 disable the 80 port function. 124 config4e_2e 1 configuration register i/o port is 4e/4f. (default) 0 configuration register i/o port is 2e/2f. 7.2. hardware monitor 7.2.1 voltage for the 8-bit adc has the 8mv lsb, the maximu m input voltage of the analog pin is 2.048v. therefore the voltage under 2.048v (ex:1.5v) can be di rectly connected to these analog inputs. the voltage higher than 2.048v should be reduced by a factor with external resistors so as to obtain the input range. only 3vcc is an except ion for it is main power of the F71889A. therefore 3vcc can directly connect to this chip?s power pin and need no external resistors. there are two functions in this pin with 3.3v. the first function is to supply internal analog power of the F71889A and the second function is that voltage with 3.3v is connected to internal serial resistors to monitor the +3.3v voltage. the internal serial resistors are two 150k ohm, so that the internal reduced voltage is half of +3.3v. there are four voltage inputs in the F71889A and the voltage divided formula is shown as follows: 2 1 2 v 12 r r r v vin + = + where v +12v is the analog input voltage, for example as figure 1. if we choose r1=27k, r2=5.1k, the exact input voltage for v+12v will be 1.907v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows.
sep, 2011 v0.21p -17- F71889A vin (< 2.04v) 8-bit adc with 8 mv lsb typical thermister connection r thm voltage inputs 10k, 25 c r vref 10k, 1% r 1 r2 (directly connect to the chip) 3vcc (directly connect to the chip) vin3.3 150k 150k 2n3906 typical bjt connection d+ d- vin (> 2.04v) figure 1. hardware monitor configuration pme# interrupt for voltage is shown as figure 2. voltage exceeding or going below high limit will cause an interrupt if the previous interrupt has been rese t by writing ?1? all the interrupt status register. voltage exceeding or going below low limit will result the same condition as voltage exceeding or going below high limit. ** * voltage pme# mode * *interrupt reset when interrupt status registers are written 1 ( level mode ) (p ulse mode ) * * * * figure 2 7.2.2 temperature the F71889A monitors three remote temperature sens ors. these sensors can be measured from -40c to 127c. more detail please refer to the register description. table 1. remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906
sep, 2011 v0.21p -18- F71889A table 2. display range is from -40c to 127c in 2?s complement format. temperature digital output -40c 1101 1000 -1c 1111 1111 1c 0000 0001 90c 0101 1010 127c 1111 1111 open 1000 0000 monitor temperature from ?thermistor? the F71889A can connect three thermistors to measure environment temperature or remote temperature. the specification of thermistor should be considered to (1) value is 3435k (2) resistor value is 10k ohm at 25c. in the figure 7-1, the ther mistor is connected by a serial resistor with 10k ohm, thenand then connected to vref. monitor temperature from ?thermal diode? also, if the cpu, gpu or external circuits pr ovide thermal diode for temperature measurement, the F71889A is capable to these situations. the bu ild-in reference table is for pnp 2n3906 transistor, and each different kind of thermal diode should be matched with specific offset and bjt gain. in the figure 7-1, the transistor is directly connected into temperature pins. adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise rejection; ther efore, careful pcb board layout and suitable external filtering are required for high-accuracy remote me asurement in electronically noisy environment. high frequency emi is best filtered at d+ and d- with an external 2200pf or 3300pf capacitor. too high capacitance may introduce errors due to the rise ti me of the switched current source. nearly all noise sources tested cause the adc measurement to be higher than the actual temperature, depending on the frequency and amplitude. monitor temperature from ?smbus device? F71889A provides smbus block read/write comp atible platform control hub (pch) ec smbus protocol, and provides byte read/write protoc ol to read cpu and chipset thermal temperature
sep, 2011 v0.21p -19- F71889A information. for byte read /write protocol, f718 89a supports 4-suit device address to read or write from the device information. for block read/write, f7188 9a supports 1 suit of device address and maximum 17 byte count for read protocol to read from the device information, and 4 byte count for write protocol to write information to device. monitor temperature from ?peci? F71889A supports intel peci3.0 interface to read temperature from peci device. over temperature signal (ovt#) ovt# alert for temperature is shown as figure 7-3. when monitored temperature exceeds the over-temperature threshold value, ovt# will be asserted unt il the temperature goes below the hysteresis temperature. t hyst tovt ovt# figure 3 temperature pme# pme# interrupt for temperature is shown as figur e 7-4. temperature exceeding high limit or going below hysteresis will cause an interrupt if the previo us interrupt has been rese t by writing ?1? all the interrupt status register.
sep, 2011 v0.21p -20- F71889A *interrupt reset when interrupt status registers are written 1 pme# to t hyst (pulse mode) (level mode active low) * * * * figure 4 7.2.3 fan fan speed count inputs are provided by the signals from fans equipp ed with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer outputs are over the 5v, the ex ternal trimming circuit should be added to reduce the voltage to obtain the input specification. the no rmal circuit and trimming circuits are shown as follows: determine the fan counter according to: rpm 10 5 . 1 count 6 = in other words, the fan speed counter (12 bit re solution) has been read from register, the fan speed can be evaluated by the following equation. count 10 5 . 1 rpm 6 = as for fan, it would be best to use 2 pulses (4 phases fan) tachometer output per round. so the parameter ?count? under 5 bit filter is 4096~64 and rpm is 366~23438 based on above equation. if using 8 phases fan, rpm would be from 183~11719. fan speed control the F71889A provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle
sep, 2011 v0.21p -21- F71889A dac fan control the range of dc output is 0~vcc, controlled by 8-bit register. 1 lsb is about 0.013v (vcc=3.3v). the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 256 value register 8bit programmed vcc (v) tage output_vol = and the suggested application circuit for linear fan control would be: fanin monitor dc output voltage +12v r10k 1 2 3 jp1 con3 r 10k r 3.6k d1 1n4148 3 2 1 8 4 + - u1a lm358 r27k r 4.7k c 47u q1 pmos c 0.1u r 4.7k figure 5 dac fan control application circuit pwm duty fan control the duty cycle of pwm can be programmed by an 8-bi t register. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle =
sep, 2011 v0.21p -22- F71889A +12v fan r1 r2 nmos pnp transistor c + - d s g figure 6 +12/5v pwm fan control application circuit fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2. auto mode (stage & linear). more detail, please refer to the description of registers & below figure. figure 7 fan type & mode selection flow start step1: select fan_type (cr94) dac (linear) pwm manual mode auto mode step2 :select fan_mode cr96 [5:4] fan3 cr96 [3:2] fan2 cr96 [1:0] fan1 step3: set rpm fan1 :cr a2,a3 fan2 :cr b2,b3 fan3 :cr c2,c3 step3: set duty fan1 :cr,a3 fan2 :cr b3 fan3 :cr c3 rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf start step1: select fan_type (cr94) dac (linear) pwm manual mode auto mode step2 :select fan_mode cr96 [5:4] fan3 cr96 [3:2] fan2 cr96 [1:0] fan1 step3: set rpm fan1 :cr a2,a3 fan2 :cr b2,b3 fan3 :cr c2,c3 step3: set duty fan1 :cr,a3 fan2 :cr b3 fan3 :cr c3 rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf rpm duty step4: set h/w monitor fan1 ? (boundary :cr a6~a9) (speed : cr aa ~ ae) fan2 ?(boundary :cr b6~b9) (speed : cr ba ~ be) fan3 ?(boundary :cr c6~c9) (speed : cr ca ~ ce) step3: set temp. follows fan1 :craf fan2 :crbf fan3 :crcf
sep, 2011 v0.21p -23- F71889A ? manual mode for manual mode, it generally acts as software fan speed control. ? auto mode in auto mode, the F71889A provides automatic fa n speed control related to temperature variation of cpu/gpu or the system. the f 71889a can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. all these values should be set by bios first. take fan1 for example, the 4 temperature boundaries could be set from register 0xa6 to 0xa9 and the five intervals for fan speed control could be set from regi ster 0xaa to 0xae. and the hysteresis setting (0 ~ 15c) could also be found in register 0x98. there are two kinds of auto mode: stage auto mode and linear auto mode. the ?fan1_interpolation_en? in register 0xafh is used for linear auto mode enable. the following examples explain the differences for stage auto mode and linear auto mode. stage auto mode in this mode, the fan keeps in a same speed for each temperature interval. and there are two types of fan speed setting: pwm duty and rpm %. a. stage auto mode (pwm duty) set temperature as 70c, 60c, 50c, 40 c and the duty as 100%, 90%, 80%, 70%, 60% figure 8 stage mode fan control illustration-2 a. once the temperature is under 40c, the lowest fan speed keeps in the 60% pwm duty.
sep, 2011 v0.21p -24- F71889A b. once the temperature is over 40c, 50cand 60c, the fan speed will vary from 70%, 80% to 90% pwm duty and increasing with the temperature level. c. for the temperature higher than 70c, the fan speed keeps in 100% pwm duty. d. if set the hysteresis is 3c (default 4c), onc e the temperature becomes lower than 67c, the fan speed would reduce to 90% pwm duty. b. stage auto mode (rpm%) set the temperature as 70c, 60c, 50c, 40 c and the corresponding f an speed is 6,000 rpm, 5,400 rpm, 4,800 rpm, 4,200 rpm, and 3,600 rpm (assume the max fan speed is 6,000 rpm). figure 9 stage mode fan control illustration-3 a. once the temperature is lower than 40c, the lowest fan speed keeps in 3,600 rpm (60% of full speed). b. once the temperature is higher than 40c, 50 c and 60c, the fan speed w ill vary from 4,200 rpm to 5,400 rpm and increasing with the temperature level. c. for the temperature higher than 70c, the fan speed keeps in the full speed 6,000 rpm. d. if the hysteresis is set as 3c (default 4c), once temperature gets lowe r than 67c, the fan speed would reduce to 5,400 rpm. linear auto mode F71889A also supports linear auto mode. the fan speed would increase or decrease linearly with the temperature. there are also pw m duty and rpm% modes for it.
sep, 2011 v0.21p -25- F71889A a. linear auto mode (pwm duty) set the temperature as 70c, 60c, 50c and 40 c and the duty is 100%, 80%, 70%, 60% and 50%. figure 10 linear mode fa n control illustration-1 a. once the temperature is lower than 40c, the lowest fan speed keeps in the 50% pwm duty b. once the temperature becomes higher than 40c , 50c and 60c, the fan speed will vary from 50% to 80% pwm duty linearly with the tempreat ure variation. the temp.-fan speed monitoring flash interval is 1sec. c. once the temperature goes over 70c, the fan speed will directly increase to 100% pwm duty (full speed). d. if set the hysteresis is 5c (default is 4c) , once the temperature becomes lower than 65c (instead of 70c), the fan speed will reduce fr om 100% pwm duty and decrease linearly with the temperature. b. linear auto mode (rpm%) set the temperature as 70c, 60c, 50c, 40 c and the corresponding f an speed is 6,000 rpm, 4,800 rpm, 4,200 rpm, 3,600 rpm and 3,000 rpm (a ssume the max fan speed is 6,000 rpm).
sep, 2011 v0.21p -26- F71889A figure 11 linear mode fan control illustration-2 a. once the temperature is lower than 40c, the lowest fan speed keeps in 3,000 rpm (50% of full speed). b. once the temperature is over 40c,50c and 60 c, the fan speed will vary from 3,000 to 4,800 rpm almost linearly with the temperature variat ion because the temp.-fan speed monitoring flash interval is 1sec. c. once the temperature goes over 70c, the f an speed will directly increase to full speed 6,000 rpm. d. if the hysteresis is 5c (default is 4c), once the temperature becomes lower than 65c (instead of 70c), the fan speed wull reduce from full spe ed and decrease linearly with the temperature. pwmout duty-cycle operating process in both ?manual rpm? and ?temperature rpm? modes, the F71889A adjust pwmout duty-cycle according to current fan count and expect ed fan count. it will operate as follows: (1). when expected count is 0xfff, pwmout duty -cycle will be set to 0x00 to turn off fan. (2). when expected count is 0x000, pwmout duty- cycle will be set to 0xff to turn on fan with full speed. (3). if both (1) and (2) are not true, (4). when pwmout duty-cycle decrease to min_duty( 00h), obviously the duty-cycle will decrease to 00h. then the F71889A will keep dut y-cycle at 00h for 1.6 seconds. after that,
sep, 2011 v0.21p -27- F71889A the F71889A starts to compare current fan count and expected count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the period, the F71889A will ignore it. start duty stop duty figure 12 fan speed control with multi-temperature. F71889A supports multi-temperature for one fan cont rol. each fan can be controlled up to 8 kinds of temperature inputs: (1) d1+ te mperature (2) d2+ te mperature (3) d3+ temperature (4) peci temperature (5) 4 suits ibx temperatures. each f an would make the maximum temperature comparison form those inputs with the expected speed, and de cide the suitable fan speed. please refer below figure 7-13. figure 13 relative temperature fan control this function works with linear auto mode which can extend to two linear slopes for one fan control (for fan 1 only). as below graph shows, this machine can support more silence fan expected speed1 expected speed 2 fan1 fan2 d2+ t (t2) d1+ t (t1) peci d3+ t (t3) ibx byte1 ibx byte3:2 ibx byte4 ibx byte5 expeted speed 3 fan3
sep, 2011 v0.21p -28- F71889A control in low temperature and high fan speed in high temperature segment. more detail setting please refers to the related registers. figure 14 in the figure below, tfan1 is the scaled temperature for fan1. t1 is the real temperature for the fan1 sensor. ta is another temperature data which can be used for linearly scale up or scale down the fan1 speed curve. tb would be the point which starts the temperature scaling. the slope for the temperature curve over and under tb would be ctup and ctdn. figure 15
sep, 2011 v0.21p -29- F71889A in application, we can set the ta as the 2 nd sensor temperature and tb as the temperature which starts the scaling. so if the 2 nd sensor temperature ta is higher or lower than tb, the fan1 speed would be changed with it. ex: ta = t1, tb = 60, ctu = 1, ctd = 1/4 figure 16 fan_fault# fan_fault# will be asserted when the fan speed does n?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there are tw o conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan spe ed count can?t reach the fan expected count in time. fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% figure 17 fan_fault# event
sep, 2011 v0.21p -30- F71889A (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count still in 0xfff. over voltage protection F71889A ovp/uvp protection function could protect the damage from voltage spikes via over voltage & under voltage protection (ovp & uvp) function. hardware strapping pin 5 default is disabled alarm mode. voltage protection function is enabled via setting the related register. when force mode occurs, the system would shut down and then can not boot at all. only re-plugging the power code (cut off vsb) could re-activate or re-boot the system at the force mode. please see below table for detail information: 7.3. hardware monitor register the F71889A implement the intel peci/sst interface and amd tsi interface to collect the cpu temperature for fan control. the cpu temperature source could be programmed to be from external diode, intel peci interface or amd tsi interface. device registers: the following is a register map order which shows a summary of all registers. please refer to each register if you need more detail information. register cr01 ? configuration registers register cr02 ~ cr03 ? protection mode & case open status registers register cr04 ? debug port temp. registers register cr07 ? peci/sst/tsi configuration registers register cr08 ? tsi control registers register cr09 ? tsi offset registers register cr0a ~ cr0f ? peci/sst/voltage registers register cr10 ~ cr3f ? voltage setting registers register cr40 ~ cr4f ? peci 3.0 command & registers register cr60 ~ cr8e ? temperature setting registers register cr90 ~ crcf ? fan control setting registers ? fan1 detail setting cra0 ~ craf ? fan2 detail setting crb0 ~ crbf ? fan3 detail setting crc0 ~ crcf register cre0 ~ cref ? tsi temperature registers register cr5a ~ cr5d ? hw chip id and vender id registers
sep, 2011 v0.21p -31- F71889A configuration register ? index 01h bit name r/w default description 7 beta_en r/w 1 0: disable the t1 beta compensation. 1: enable the t1 beta compensation. 6 intel_model r/w 1 0: amd tsi model. 1: intel model. 5 tsi_en r/w 0 0: disable the tsi function via peci/sst pins. 1: enable the tsi function via peci/sst pins. this bit accompanying with intel_model and sst_en will determine the availability of amd tsi, intel pch smbus, peci and sst (this bit is cleared by lreset#). see below table: 4-3 reserved - - reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperatur e and voltage monitoring operations; a zero puts the part in standby mode. protection mode configuration register ? index 02h bit name r/w default description 7 reserved r/w 0 dummy register. 6 case_beep_en r/w 0 0: disable case open event output via beep. 1: enable case open event output via beep.
sep, 2011 v0.21p -32- F71889A 5-4 ovt_mode r/w 0 00: the ovt# will be low active level mode. 01: the ovt# will be low pulse mode. (200us low pulse). 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 sst_ invert r/w 0 0:normal sst 1:sst_invert 2 case_smi_en r / w 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 alert_mode r/w 0 00: the alert# will be low active level mode. 01: the alert# will be high active level mode. 10: the alert# will indicate by 1hz led function. 11: the alert# will indicate by (400/800hz) beep output. case status register ? index 03h bit name r/w default description 7-1 reserved r/w 0 return 0 when read. 0 case_sts r/w 1 case open event status, wr ite 1 to clear if case open event cleared. debug port temp register ? index 04h bit name r/w default description 7-2 reserved r/w 0 return 0 when read. 1-0 dport_temp_sel r/w 01 debug port temperature source select: 00: 0xff. 01: t1 reading. 10: t2 reading. 11: t3 reading. peci/sst/tsi configuration register ? index 07h bit name r/w default description 7-5 reserved r/w 0 return 0 when read. 4 dig_t1_sel r/w 0 this bit is used to select amd tsi/inte l ibx or peci to be the t1 temperature when new_mode_en is set to 1. 3 ibx_alt_en r/w 0 this bit is used to control the am d tsi/intel ibx/peci function. (see configuration register 0x00) 2 peci_en r/w 0 this bit is used to control the am d tsi/intel ibx/peci function. (see configuration register 0x00) 1 new_mode_en r/w 0 this bit is used to control the am d tsi/intel ibx/peci function. (see configuration register 0x00) 0 new_tsi_en r/w 0 this bit is used to control the am d tsi/intel ibx/peci function. (see configuration register 0x00) tsi control register ? index 08h bit name r/w default description 7 reserved - 0 reserved. 6 tsi_offset_sel r/w 0 set this bit to select the offset of amd tsi/intel ibx. 0: tcc_temp in cr0c 1: tsi_offset in cr09 5-4 reserved - 0 reserved.
sep, 2011 v0.21p -33- F71889A 3 tsi 02_sel r/w 0 if this bit is set to 1, cr7b is able to be written and can also be used to control fan. 2 tsi 01_sel r/w 0 if this bit is set to 1, cr7a is able to be written and can also be used to control fan. 1-0 reserved - 0 reserved. tsi offset register ? index 08h bit name r/w default description 7-0 tsi_offset r/w 0 when peci and amd tsi/intel ibx are enabled at the same time, this byte is used as the offset to be added to the cpu temperature reading of amd_tsi/intel ibx. to usin g this byte as offset of amd tsi/intel ibx cpu temperature reading, the tsi_offset_sel in cr08 must be set to 1. the range of this register is -128 ~ 127. sst and vtt_sel register ? index 0ah bit name r/w default description 7-5 reserved - 0 reserved. 4 sst_en_reg r/w 0 set this bit ?1? and select intel model will enable sst interface. otherwise will disable sst interface this bit is cleared by lreset#. 3-2 vtt_sel r/w 0 peci (vtt) voltage select. 00: vtt is 1.23v 01: vtt is 1.13v 10: vtt is 1.00v 11: vtt is 1.00v 1 dig_t1_en r/w 0 0: disable the digital interface of t1 (peci/tsi). 1: enable the digital interface of t1. 0 diode_t1_en r/w 1 0: disable the d1+ measurement. 1: enable the d1+ measurement. peci address register ? index 0bh bit name r/w default description 7-4 cpu_sel r/w 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping() command to find cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 1, i.e. peci address is 0x31. 0100: cpu is in socket 2, i.e. peci address is 0x32. 1000: cpu is in socket 3, i.e. peci address is 0x33. otherwise are reserved. 3-1 reserved - 0 reserved. 0 domain1_en r/w 0 if the cpu selected is dual core. set this register 1 to read the temperature of domain1.
sep, 2011 v0.21p -34- F71889A tcc temp register ? index 0ch bit name r/w default description 7-0 tcc_temp/tsi_off set r/w 8?h55 tcc activation temperature/tsi offset. when peci is enabled, the absolute value of cpu temperature is calculated by the equation: cpu_temp = tcc_temp + peci reading. the range of this register is -128 ~ 127. when amd tsi or intel pch smbus is enabled, this byte is used as the offset to be added to the reading. sst addr register ? index 0dh bit name r/w default description 7-0 sst_addr/ smbus_addr r/w 8?h4c when amd tsi or intel pch smbus is enabled, this byte is used as smbus_addr. smbus_addr [7:1] is the slave address sent by the embedded master to fetch the temperature. otherwise, this byte is used as sst_addr if sst is enabled. voltage div register ? index 0eh bit name r/w default description 7-6 vin4_div r/w 0 the value indicates the divisor of the voltage source. 00: voltage source is directly connected to vin4. 01: voltage source is divided by 2 and connected to vin4. 10: voltage source is divided by 4 and connected to vin4. 11: voltage source is divided by 16 and connected to vin4. 5-4 vin3_div r/w 0 the value indicates the divisor of the voltage source. 00: voltage source is directly connected to vin3. 01: voltage source is divided by 2 and connected to vin3. 10: voltage source is divided by 4 and connected to vin3. 11: voltage source is divided by 16 and connected to vin3. 3-2 vin2_div r/w 0 the value indicates the divisor of the voltage source. 00: voltage source is directly connected to vin2. 01: voltage source is divided by 2 and connected to vin2. 10: voltage source is divided by 4 and connected to vin2. 11: voltage source is divided by 16 and connected to vin2. 1-0 vin1_div r/w 0 the value indicates the divisor of the voltage source. 00: voltage source is directly connected to vin1. 01: voltage source is divided by 2 and connected to vin1. 10: voltage source is divided by 4 and connected to vin1. 11: voltage source is divided by 16 and connected to vin1. above is available only if sst is enabled. otherwise, bit 7-1 will be used as i2c_addr if intel pch smbus is enabled. peci config. and voltage register ? index 0fh bit name r/w default description 7-4 reserved reserved. 3-2 vin6_div r/w 0 the value indicates the divisor of the voltage source. 00: voltage source is directly connected to vin6. 01: voltage source is divided by 2 and connected to vin6. 10: voltage source is divided by 4 and connected to vin6. 11: voltage source is divided by 16 and connected to vin6.
sep, 2011 v0.21p -35- F71889A 1-0 vin5_div r/w 0 the value indicates the divisor of the voltage source. 00: voltage source is directly connected to vin5. 01: voltage source is divided by 2 and connected to vin5. 10: voltage source is divided by 4 and connected to vin5. 11: voltage source is divided by 16 and connected to vin5. vin6_div[0] and vin5_div are used as tsi_temp_sel[2:0] if intel pch smbus is enabled. tsi_temp_sel is used to select the temperature source for fan control. tsi_temp_sel temperature source 000 maximum of mch or cpu 001 pch 010 cpu 011 mch 100 dimm0 101 dimm1 110 dimm2 111 dimm3 7.3.1 voltage setting voltage pme# enable register ? index 10h bit name r/w default description 7-2 reserved -- 0 reserved 6 v6_vp_en r/w 0 set this bit 1 to enable v6 voltage-protection event. 5 v5_vp_en r/w 0 set this bit 1 to enable v5 voltage-protection event. 4-2 reserved -- 0 reserved 1 en_v1_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for vin1. 0 3vcc_vp_en r/w 0 set this bit 1 to enable 3vcc voltage protection event. voltage1 interrupt status register ? index 11h bit name r/w default description 7-2 reserved -- 0 reserved 1 v1_ exc _sts r/w 0 this bit is set when the vin1 is over t he high limit. write 1 to clear this bit, write 0 will be ignored. 0 vp_sts wc 0 this bit is voltage-protection status. once one of the monitored voltages (3vcc, vin5, vin6) over its related over-voltage limits or under its related under-voltage limits, if the related voltage-protection shut down enable bit is set, this bit will be set to 1. write 1 to this bit will clear it to 0. (this bit is powered by vbat) voltage1 exceeds real time status register 1 ? index 12h bit name r/w default description 7-2 reserved -- 0 reserved 1 v1_exc ro 0 a one indicates vin1 exceeds the high or low limit. a zero indicates vin1 is in the safe region. 0 reserved -- 0 reserved
sep, 2011 v0.21p -36- F71889A voltage1 beep enable register ? index 13h bit name r/w default description 7-2 reserved -- 0 reserved 1 en_v1_beep r/w 0 a one enables the corresponding interr upt status bit for beep output of vin1. 0 reserved -- 0 reserved voltage-protection enable register ? index 14h bit name r/w default description 7 reserved -- 0 reserved 6 v6_vp_en r 0 set this bit 1 to enable v6 voltage-protection event. 5 v5_vp_en r 0 set this bit 1 to enable v5 voltage-protection event. 4-1 reserved -- 0 reserved 0 3vcc_vp_en r 0 set this bit 1 to enable 3vcc voltage-protection event. voltage protection event status register ? index 15h bit name r/w default description 7-1 reserved -- 0 reserved 0 v_exc_vp r/wc 0 this bit is voltage-protection status . once one of the monitored voltages (3vcc, vin5, vin6) over its related over-voltage limits or under its related under-voltage limits, if the related vo ltage-protection shut down enable bit is set, this bit will be set to 1. write 1 to this bit will clear it to 0. (this bit is powered by vbat) voltage-protection configuration register (powered by vbat) ? index 16h bit name r/w default description 7-4 reserved - - reserved. 3-2 pu_time r/w 01 pson# de-active time select in alarm mode of voltage protection. 00: pson# tri-state 0.5 sec and then inve rted of s3# when over voltage or under voltage occurs. 01: pson# tri-state 1 sec and then inve rted of s3# when over voltage or under voltage occurs. 10: pson# tri-state 2 sec and then inve rted of s3# when over voltage or under voltage occurs. 11: pson# tri-state 4 sec and then inve rted of s3# when over voltage or under voltage occurs.
sep, 2011 v0.21p -37- F71889A 1-0 vp_en_delay r/w 10 vp_en_delay could set the delay time to start voltage protecting after vdd power is ok when ovp_mode is 1. (ovp_mode is strapped by sout2 pin) 00: bypass 01: 50ms 10: 100ms 11: 200ms voltage protection power good select register ? index 3fh bit name r/w default description 7-1 reserved -- 0 reserved 0 ovp_rst_sel r/w 0 0: ovp/uvp power good signal is vdd3vok (vcc3v > 2.8v) 1: ovp/uvp power good signal is pwrok. ovp/uvp function wont? start detec ting until power good is ready. voltage reading and limit ? index 20h- 3fh address attribute default value description 20h ro -- 3vcc reading. the unit of reading is 8mv. 21h ro -- vin1 (vcore) reading. the unit of reading is 8mv. 22h ro -- vin2 reading. the unit of reading is 8mv. 23h ro -- vin3 reading. the unit of reading is 8mv. 24h ro -- vin4 reading. the unit of reading is 8mv. 25h ro -- vin5 reading. the unit of reading is 8mv. 26h ro -- vin6 reading. the unit of reading is 8mv. 27h ro -- i_vsb3v reading. t he unit of reading is 8mv. 28h ro -- vbat reading. the unit of reading is 8mv. 29~2ch ro ff reserved 2dh ro -- this byte indicates current fan1 duty. 2eh ro -- this byte indicates current fan2 duty. 2fh ro -- this byte indicates current fan3 duty. 30h r/w 7a 3vcc under-voltage limit (v0_uvv_limit). the unit is 9mv (this byte is powered by vbat) 31h r/w d7 3vcc over-voltage protection limit. the unit is 9 mv 32h r/w ff v1 high limit setting register. the unit is 8mv. 33~35h ro ff reserved. 36h r/w c9 v5 over-voltage protection limit. the unit is 9 mv 37h r/w c8 v6 over-voltage protection limit. the unit is 9 mv 38h r/w 75 vin5 under-voltage limit (v5_uvv_limit). t he unit is 9mv (this byte is powered by vbat) 39h r/w 85 vin6 under-voltage limit (v6_uvv_limit). t he unit is 9mv (this byte is powered by vbat) 38-3eh ro ff reserved. 3fh r/w 0 set bit 0 to ?1? to select ovp start monitor after pwrok ready.
sep, 2011 v0.21p -38- F71889A 7.3.2 peci 3.0 command and register peci configuration register ? index 40h bit name r/w default description 7 rdiamsr_cmd_en r/w 0 when peci temperature monitoring is enabled, set this bit 1 will generate a rdiamsr () command before a gettemp () command. 6 c3_update_en r/w 0 if rdiamsr_cmd_en is not set to 1, the temperature data is not allowed to be updated when the completion code of rdiamsr () is 0x82. 5-4 reserved r - reserved 3 c3_ptemp_en r/w 0 set this bit 1 to enable updateing posit ive value of tem perature if the completion code of rdiamsr () is 0x82. 2 c0_ptemp_en r/w 0 set this bit 1 to enable updating positive value of temperature if the completion code of rdiamsr () is not 0x82 and the bit 8 of completion code is not 1 either. 1 c3_all0_en r/w 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr () is 0x82. 0 c0_all0_en r/w 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr () is not 0x82 and the bit 8 of completion code is not 1 either. peci master control register ? index 41h bit name r/w default description 7 peci_cmd_start w - write 1 to this bit to start a peci command when using as a peci master. (peci_pending must be set to 1) 6-5 reserved r - reserved 4 peci_pending r/w 0 set this bit 1 to stop monitoring peci temperature. 3 reserved r - reserved 2-0 peci_cmd r/w 3?h0 peci command to be us ed by peci master. 000: ping() 001: getdib() 010: gettemp() 011: rdiamsr() 100: rdpkgconfig() 101: wrpkgconfig() others: reserved peci master status register ? index 42h bit name r/w default description 7-3 reserved r - reserved 2 abort_fcs r/wc - this bit is the abort fcs status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 1 peci_fcs_err r/wc - this bit is the fcs error status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 0 peci_finish r/wc - this bit is the command finish stat us of peci master commands. write this bit 1 or read this byte will clear this bit to 0. peci master data0 register ? index 43h bit name r/w default description 7-0 peci_data0 r/w 0 for rdiamsr (), rdpkgconfig () and wrpkgconfig () command, this byte represents ?host id [7:1] & retry [0 ]?. please refer to peci interface specification for more detail.
sep, 2011 v0.21p -39- F71889A peci master data1 register ? index 44h bit name r/w default description 7-0 peci_data1 r/w 0 for rdiamsr (), this byte represents ?processor id?. for rdpkgconfig () and wrpkgconfig (), this byte represents ?index?. please refer to peci interface specification for more detail. peci master data2 register ? index 45h bit name r/w default description 7-0 peci_data2 r/w 0 for rdiamsr (), this byte is the least significant byte of ?msr address?. for rdpkgconfig () and wrpkgconfig (), this byte is the least significant byte of ?parameter?. please refer to peci interface specification for more detail. peci master data3 register ? index 46h bit name r/w default description 7-0 peci_data3 r/w 0 for rdiamsr (), this byte is the most significant byte of ?msr address?. for rdpkgconfig () and wrpkgconfig (), this byte is the most significant byte of ?parameter?. please refer to peci interface specification for more detail. peci master data4 register ? index 47h bit name r/w default description 7-0 peci_data4 r/w 0 for getdib() , this byte represents ?device info? for gettemp (), this byte represents the least significant byte of temperature. for rdiamsr () and rdpkgconfig () , this byte is ?completion code?. for wrpkgconfig (), this byte represents ?data[7:0]? peci master data5 register ? index 48h bit name r/w default description 7-0 peci_data5 r/w 0 for getdib () , this byte represents ?revision number? for gettemp (), this byte represents the most significant byte of temperature. for rdiamsr () and rdpkgconfig () , this byte represents ?data[7:0]? for wrpkgconfig (), this byte represents ?data[15:8]? peci master data6 register ? index 49h bit name r/w default description 7-0 peci_data6 r/w 0 for rdiamsr () and rdpkgconfig (), this byte represents ?data[15:8]?. for wrpkgconfig (), this byte represents ?data [23:16]? peci master data7 register ? index 4ah bit name r/w default description 7-0 peci_data7 r/w 0 for rdiamsr () and rdpkgconfig (), this byte represents ?data[23:16]?. for wrpkgconfig (), this byte represents ?data[31:24]? peci master data8 register ? index 4bh bit name r/w default description 7-0 peci_data8 r/w 0 for rdiamsr () and rdpkgconfig () , this byte represents ?data[31:24]?. for wrpkgconfig(), this byte represents ?aw fcs?
sep, 2011 v0.21p -40- F71889A peci master data9 register ? index 4ch bit name r/w default description 7-0 peci_data9 r/w 0 for rdiamsr (), this byte represents ?data [39:32]?. for wrpkgconfig(), this byte represents ?completion code? peci master data10 register ? index 4dh bit name r/w default description 7-0 peci_data10 r/w 0 for rdiamsr (), th is byte represents ?data [47:40]?. peci master data11 register ? index 4eh bit name r/w default description 7-0 peci_data11 r/w 0 for rdiamsr (), this byte represents ?data [55:48]?. peci master data12 register ? index 4fh bit name r/w default description 7-0 peci_data12 r/w 0 for rdiamsr (), th is byte represents ?data [63:56]?. 7.3.3 temperature setting temperature pme# enable register ? index 60h bit name r/w default description 7 en_ t3_ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp3 exceeds ovt limit setting. 6 en_ t2_ ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds ovt setting. 5 en_ t1_ ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds ovt setting. 4 reserved r/w 0 reserved 3 en_ t3_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp3 exceeds high limit setting. 2 en_ t2_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved temperature interrupt status register ? index 61h bit name r/w default description 7 t3_ovt_sts r/w 0 a one indicates temp3 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 6 t2_ovt _sts r/w 0 a one indicates temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. writ e 1 to clear this bit, write 0 will be ignored. 5 t1_ovt _sts r/w 0 a one indicates temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored. 4 reserved r/w 0 reserved 3 t3_exc _sts r/w 0 a one indicates temp3 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored.
sep, 2011 v0.21p -41- F71889A 2 t2_exc _sts r/w 0 a one indicates temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 1 t1_exc _sts r/w 0 a one indicates temp1 temperature s ensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 0 reserved r/w 0 reserved temperature real time status register ? index 62h bit name r/w default description 7 t3_ovt r/w 0 set when the temp3 exceeds the ovt limit. clear when the temp3 is below the ?ovt limit ?hysteresis? temperature. 6 t2_ovt r/w 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature. 5 t1_ovt r/w 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 reserved r/w 0 reserved 3 t3_exc r/w 0 set when the temp3 exceeds the high limit. clear when the temp3 is below the ?high limit ?hysteresis? temperature. 2 t2_exc r/w 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 reserved r/w 0 reserved temperature beep enable register ? index 63h bit name r/w default description 7 en_ t3_ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp3 exceeds ovt limit setting. 6 en_ t2_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 reserved r/w 0 reserved 3 en_ t3_exc_beep r/w 0 if set this bit to 1, beep signal wi ll be issued when temp3 exceeds high limit setting. 2 en_ t2_exc_beep r/w 0 if set this bit to 1, beep signal wi ll be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 0 if set this bit to 1, beep signal wi ll be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved ovt output enable register 1 ? index 66h bit name r/w default description 7 en_t3_alert r 0 enable temperature 3 alert event (a sserted when temperature over high limit) 6 en_t2_alert r 0 enable temperature 2 alert event (a sserted when temperature over high limit) 5 en_t1_alert r 0 enable temperature 1 alert event (a sserted when temperature over high limit)
sep, 2011 v0.21p -42- F71889A 4 reserved r 0 reserved. 3 en_t3_ovt r/w 0 enable over temperature (ovt ) mechanism of temperature3. 2 en_t2_ovt r/w 0 enable over temperature (ovt ) mechanism of temperature2. 1 en_t1_ovt r/w 1 enable over temperature (ovt ) mechanism of temperature1. 0 reserved r 0h reserved. temperature sensor type register ? index 6bh bit name r/w default description 7-4 reserved ro 0 reserved 3 t3_mode r/w 1 0: temp3 is connected to a thermistor 1: temp3 is connected to a bjt (default). 2 t2_mode r/w 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt (default). 1 t1_mode r/w 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt (default). 0 reserved r 0h -- temp1 limit hystersis select register -- index 6ch bit name r/w default description 7-4 temp1_hys r/w 4h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). 3-0 reserved r 0h -- temp2 and temp3 limit hystersis select register -- index 6dh bit name r/w default description 7-4 temp3_hys r/w 2h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). 3-0 temp2_hys r/w 4h limit hysteresis. (0~15 o c) temperature and below the (boundary ? hysteresis). diode open status register -- index 6fh bit name r/w default description 7-4 reserved ro 0h reserved 3 t3_diode_open ro 0h external diode 3 is open or short 2 t2_diode_open ro 0h external diode 2 is open or short 1 t1_diode_open ro 0h this register indicates the abnorma lity of temperature 1 measurement. when tsi interface is enabled, it indicates the error of not receiving nack bit or a timeout occurred. when peci interface is enabled, it indicates an error code (0x0080 or 0x0081) is received from peci slave. when external diode is used, it indicates the bjt is open or short. 0 reserved r 0h -- temperature ? index 70h- 8fh address attribute default value description 70h reserved ffh reserved 71h reserved ffh reserved 72h ro -- temperature 1 reading. t he unit of reading is 1 o c.at the moment of reading this register.
sep, 2011 v0.21p -43- F71889A 73h ro -- reserved 74h ro -- temperature 2 reading. t he unit of reading is 1 o c.at the moment of reading this register. 75h ro -- reserved 76h ro -- temperature 3 reading. t he unit of reading is 1 o c.at the moment of reading this register. 77h ro -- reserved 78h ro -- peci temperature reading 79h ro -- amd tsi or intel ibx temperature reading 7ah ro -- the raw data of t3 read from digital interf ace. (only available if intel ibx interface is enabled) 7bh ro -- the raw data of t2 read from digital interf ace. (only available if intel ibx interface is enabled) 7ch ro -- the data of t1 r ead from digital interface. 7dh ro -- the raw data of t1 read from d1+. 7eh r/w 00h- t1 slope adjust. 7fh r/w 00h t1 source select. 80h reserved ffh reserved 81h reserved ffh reserved 82h r/w 64h temperature sensor 1 ovt limit. the unit is 1 o c. 83h r/w 55h temperature sensor 1 high limit. the unit is 1 o c. 84h r/w 64h temperature sensor 2 ovt limit. the unit is 1 o c. 85h r/w 55h temperature sensor 2 high limit. the unit is 1 o c. 86h r/w 55h temperature sensor 3 ovt limit. the unit is 1 o c. 87h r/w 46h temperature sensor 3 high limit. the unit is 1 o c. 88-8bh ro -- reserved 8c~8dh ro ffh reserved t1 slope adjust register -- index 7eh bit name r/w default description 7 dig_t1_add r/w 0h this bit is the sign bit for digital t1 reading slope adjustment. see dig_t1_scale below for detail.
sep, 2011 v0.21p -44- F71889A 6-4 dig_t1_scale r/w 0h accompanying with dig_t1_add, the slope adjustment of digital t1 is listed. dig_t1_add dig_t1_scale slope 0 000 no adjustment 0 001 1/2 0 010 3/4 0 011 7/8 0 100 15/16 0 101 31/32 0 110 63/64 0 111 127/128 1 000 no adjustment 1 001 3/2 1 010 5/4 1 011 9/8 1 100 17/16 1 101 33/32 1 110 65/64 1 111 129/128 3 diode_t1_add r/w 0h the function of this bit is the same as dig_t1_add expect that it is for d1+ reading. 2-0 diode_t1_scale r/w 0h the function of this bit is the same as dig_t1_scale expect that it is for d1+ reading. temperature filter select register -- index 7fh bit name r/w default description 7-2 reserved - - reserved. 1-0 t1_src_sel_reg r/w 00 the bits are used when diode_t1_en and dig_t1_en are both enabled. the real select bits t1_scr_sel are fi xed to 2?b01 if diode_t1_en is ?0? and 2?b00 if dig_t1_en is ?0?. the t1 source is listed. t1_src_sel t1 source 00 from d1+ only 01 from digital reading (peci/tsi) 10 average 11 maximum temperature filter select register -- index 8eh bit name r/w default description 7-6 iir-queur3 r/w 2?b10 the queue time for third filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 5-4 iir-queur2 r/w 2?b10 the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 3-2 iir-queur1 r/w 2?b10 the queue time for first filter to quickly update values. 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. 0 reserved r - --
sep, 2011 v0.21p -45- F71889A 7.3.4 fan control setting fan pme# enable register ? index 90h bit name r/w default description 7-3 reserved ro 0h reserved 2 en_fan3_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan3. 1 en_fan2_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2. 0 en_fan1_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1. fan interrupt status register ? index 91h bit name r/w default description 7-3 reserved ro 0 reserved 2 fan3_sts r/w -- this bit is set when the fan3 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w -- this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w -- this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. fan real time status register ? index 92h bit name r/w default description 7-3 reserved -- 0 reserved 2 fan3_exc ro -- this bit set to high mean that fan3 count can?t meet expect count over than smi time (cr9f) or when duty not zero but fan stop over then 3 sec. 1 fan2_exc ro -- this bit set to high mean that fan2 count can?t meet expect count over than smi time (cr9f) or when duty not zero but fan stop over then 3 sec. 0 fan1_exc ro -- this bit set to high mean that fan1 count can?t meet expect count over than smi time (cr9f) or when duty not zero but fan stop over then 3 sec. fan beep# enable register ? index 93h bit name r/w default description 7 full_with_t3_en r/w 0 set one will enable fan to force full speed when t3 over high limit. 6 full_with_t2_en r/w 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_t1_en r/w 0 set one will enable fan to force full speed when t1 over high limit. 4 reserved r/w 0 reserved. 3 reserved - - reserved. 2 en_fan3_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. 1 en_fan2_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. 0 en_fan1_ beep r/w 0 a one enables the corresponding interrupt status bit for beep. fan type select register -- index 94h (fan_prog_sel = 0) bit name r/w default description 7-6 reserved - - reserved.
sep, 2011 v0.21p -46- F71889A 5-4 fan3_type r/w 2?b 0s 00: output pwm mode (pushpull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by rts2# 0: rts2# is pull up by internal 47k resistor. 1: rts2# is pull down by external resistor. 3-2 fan2_type r/w 2?b 0s 00: output pwm mode (pushpull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by rts2# 0: rts2# is pull up by internal 47k resistor. 1: rts2# is pull down by external resistor. 1-0 fan1_type r/w 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circuit to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by rts2# 0: rts2# is pull up by internal 47k resistor. 1: rts2# is pull down by external resistor. s : register default values are decided by trapping. fan1 base temperature register ? index 94h (fan_prog_sel = 1) bit name r/w default description 7-0 fan1_base_temp r/w 8?h0 this register is used to set the base temperature for fan1 temperature adjustment. the fan1 temperature is calculated according to the equation: tfan1 = tnow + (ta ? tb)*ct where tnow is selected by fan1_temp_sel_dig and fan1_temp_sel. tb is this register, ta is selected by tfan1_adj_sel and ct is selected by tfan1_adj_up_rate/tfan1_adj_dn_rate. to access this register, fan_prog_ sel (cr9f[7]) must set to ?1?. fan1 temperature adjustment rate register ? index 95h (fan_prog_sel = 1) bit name r/w default description 7 reserved - - reserved. 6-4 t fan1_adj_up_rate r/w 3?h0 this selects the weighting of the differen ce between ta and tb if ta is higher than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 2 reserved - - reserved.
sep, 2011 v0.21p -47- F71889A 2-0 t fan1_adj_dn_rate r/w 3?h0 this selects the weighting of the difference between ta and tb if ta is lower than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. fan mode select register -- index 96h bit name r/w default description 7-6 reserved - - reserved. 5-4 fan3_mode r/w 1h 00: auto fan speed control, fan spe ed will follow different temperature by different rpm that defines in 0xc6-0xce. 01: auto fan speed control, fan spe ed will follow different temperature by different duty cycle that defines in 0xc6-0xce. 10: manual mode fan control, user can write expected rpm count to 0xc2-0xc3, and F71889A will auto cont rol duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xc3, and F71889A will output this value duty or voltage to control fan speed. 3-2 fan2_mode r/w 1h 00: auto fan speed control, fan spe ed will follow different temperature by different rpm that defines in 0xb6-0xbe. 01: auto fan speed control, fan spe ed will follow different temperature by different duty cycle (voltage) that defines in 0xb6-0xbe. 10: manual mode fan control, user can write expected rpm count to 0xb2-0xb3, and F71889A will auto control duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, and F71889A will output this value duty or voltage to control fan speed. 1-0 fan1_mode r/w 1h 00: auto fan speed control, fan spe ed will follow different temperature by different rpm that defines in 0xa6-0xae. 01: auto fan speed control, fan spe ed will follow different temperature by different duty cycle that defines in 0xa6-0xae. 10: manual mode fan control, user can write expected rpm count to 0xa2-0xa3, and F71889A will auto control duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xa3, and F71889A will output this value duty or voltage to control fan speed. auto fan1 and fan2 boundary hystersis select register -- index 98h bit name r/w default description 7-4 fan2_hys r/w 4h 0000: boundary hysteresis. (0~15 o c) segment will change when the temperatur e over the boundary temperature and below the (boundar y ? hysteresis). 3-0 fan1_hys r/w 4h 0000: boundary hysteresis. (0~15 o c) segment will change when the temperatur e over the boundary temperature and below the (boundar y ? hysteresis).
sep, 2011 v0.21p -48- F71889A auto fan3 boundary hystersis select register -- index 99h bit name r/w default description 7-4 reserved - - reserved. 3-0 fan3_hys r/w 2h 0000: boundary hysteresis. (0~15 o c) segment will change when the temperatur e over the boundary temperature and below the (boundar y ? hysteresis). fan3 control register ? index 9ah bit name r/w default description 7-6 fan3_freq_sel - - select the pwm3 frequency 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220 hz 5-4 reserved r/w 0 reserved (keep the value of these two bits ?0?) 3-1 reserved r/w 0 reserved. 0 fan3_ext_en r/w 0 set this bit 1 to enable the function t hat fan3 output duty could be adjusted by gpio53/gpio54. auto fan up speed update rate select register -- index 9bh (fan_rate_prog_sel = 0) bit name r/w default description 7-6 reserved - - reserved. 5-4 fan3_up_rate r/w 1h fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_up_rate r/w 1h fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_up_rate r/w 1h fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz auto fan down speed update rate select re gister -- index 9bh (fan_rate_prog_sel = 1) bit name r/w default description 7-6 reserved - - reserved. 5-4 fan3_down_rate r/w 1h fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz
sep, 2011 v0.21p -49- F71889A 3-2 fan2_down_rate r/w 1h fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_down_rate r/w 1h fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w default description 7-4 fan2_stop_duty r/w 5h when fan start, the fan_ctrl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_stop_duty r/w 5h when fan start, the fan_ctrl1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). fan3 start up duty-cycle/voltage ? index 9dh bit name r/w default description 7-4 reserved - - reserved. 3-0 fan3_stop_duty r/w 5h when fan start, the fan_ctrl 3 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). fan programmable duty-cycle/voltage loaded after power -on ? index 9eh bit name r/w default description 7-0 prog_duty_val r/w 99h this byte will be immediately loaded as fan duty value after vdd is powered on if it has been programmed before shut down. fan fault time register -- index 9fh bit name r/w default description 7 fan_rate_prog_se l r/w 0 0: index 9bh is the fan up spe ed update rate select register. 1: index 9bh is the fan down s peed update rate select register. 6 reserved -- -- reservd 5 fan_neg_temp_e n r/w 0 0: disable the negative temperatur e compare of fan expected value. 1: enable the negative temperature compare of fan expected value. 4 full_duty_sel r/w -- 0: the full duty is 100%. (pull down by external resistor) 1: the full duty is 60% (default, pu ll up by internal 47k resistor). this register is power on trap by dtr1#. 3-0 f_fault_time r/w ah this register determines the time of f an fault. the condition to cause fan fault event is: when pwm_duty reaches ffh, if the fan speed count can?t reach the fan expected count in time. the unit of this register is 1 second. the default value is 11 seconds. (set to 0, means 1 second; set to 1, means 2 second; set to 2, means 3 second?) another condition to cause fan fault event is fan stop and the pwm duty is greater than the minimum duty programmed by the register index 9c-9dh.
sep, 2011 v0.21p -50- F71889A fan1 index a0h- afh address attribute default value description a0h ro 8?h0f fan1 count reading (msb). at the moment of reading th is register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h r/w 8?h00 rpm mode (cr96 bit0=0): fan1 expected speed count value (msb), in auto fan mode (cr96 bit1 ? 0) this register is auto updated by hardware. duty mode (cr96 bit0=1): this byte is reserved byte. a3h r/w 8?h01 rpm mode (cr96 bit0=0): fan1 expected speed count value (lsb) or expected pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode (cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit1 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 8?h03 fan1 full speed count reading (msb). at t he moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb). vt1 boundary 1 temperature ? index a6h bit name r/w default description 7-0 bound1tmp1 r/w 3ch (60 o c) the 1st boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 1 register (index aah). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 2 register (index abh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt1 boundary 2 temperature ? index a7 bit name r/w default description 7-0 bound2tmp1 r/w 32 (50 o c) the 2nd boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 2 register (index abh). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 3 register (index ach). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt1 boundary 3 temperature ? index a8h bit name r/w default description 7-0 bound3tmp1 r/w 28h (40 o c) the 3rd boundary temperature fo r vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 3 register (index ach). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 4 register (index adh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?.
sep, 2011 v0.21p -51- F71889A vt1 boundary 4 temperature ? index a9 bit name r/w default description 7-0 bound4tmp1 r/w 1eh (30 o c) the 4th boundary temperature fo r vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expected value will load from segment 4 register (index adh). when vt1 temperature is below this boundary ? hysteresis, fan1 expected value will load from segment 5 register (index aeh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. fan1 segment 1 speed count ? index aah bit name r/w default description 7 - 0 sec1speed1 r / w ffh (100%) the meaning of this register is depending on the fan1_mode (cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 2 speed count ? index abh bit name r/w default description 7 - 0 sec2speed1 r / w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 3 speed count ? index ach bit name r/w default description 7 - 0 sec3speed1 r / w b2h (70%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 4 speed count ? index adh bit name r/w default description 7 - 0 sec4speed1 r / w 99h (60%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan1 segment 5 speed count ? index aeh bit name r/w default description 7 - 0 sec5speed1 r / w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
sep, 2011 v0.21p -52- F71889A fan1 temperature mapping select ? index afh bit name r/w default description 7 fan1_temp_sel _dig r/w 0 this bit companying with fan1_temp_sel select the temperature source for controlling fan1. 6 reserved -- 0 reserved 5 fan1_up_t_en r / w 0 set 1 to force fan1 to full speed if any temperature over its high limit. 4 fan1_interpolation_ en r/w 0 set 1 will enable the interpol ation of the fan expect table. 3 fan1_jump_high_en r / w 0 this register controls the fan1 dut y movement when temperature over highest boundary. 0: the fan1 duty will increases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec1speed1 register. this bit only activates in duty mode. 2 fan1_jump_low_en r/w 0 this register controls the fan1 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan1 duty will decreases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec2speed1 register. this bit only activates in duty mode. 1-0 fan1_temp_sel r/w 1 this registers companying with fan1_temp_sel_dig select the temperature source for controlling fan1. the following value is comprised by {fan1_temp_sel_dig, fan1_temp_sel} 000: fan1 follows peci temperature (cr78h) 001: fan1 follows temperature 1 (cr72h). 010: fan1 follows temperature 2 (cr74h). 011: fan1 follows temperature 3 (cr76h). 100: fan1 follows amd tsi or intel ibx temperature (cr79h) 101: fan1 follows digital temperature 1 (cr7ch). 110: fan1 follows digital temperature 2 (cr7bh). 111: fan1 follows digital temperature 3 (cr7ah). otherwise: reserved. fan2 index b0h- bfh address attribute default value description b0h ro 8?h0f fan2 count reading (msb). at the moment of reading th is register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan2 count reading (lsb). b2h r/w 8?h00 rpm mode (cr96 bit2=0): fan2 expect speed count value (msb), in auto fan mode (cr96 bit3 ? 0) this register is auto updated by hardware. duty mode (cr96 bit2=1): this byte is reserved byte. b3h r/w 8?h01 rpm mode (cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode (cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 8?h03 fan2 full speed count reading (msb) . at the moment of reading this register, the
sep, 2011 v0.21p -53- F71889A lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan2 full speed count reading (lsb). vt2 boundary 1 temperature ? index b6h bit name r/w default description 7-0 bound1tmp2 r/w 3ch (60 o c) the 1st boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 1 register (index bah). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 2 register (index bbh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt2 boundary 2 temperature ? index b7 bit name r/w default description 7-0 bound2tmp2 r/w 32 (50 o c) the 2nd boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 2 register (index bbh). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 3 register (index bch). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt2 boundary 3 temperature ? index b8h bit name r/w default description 7-0 bound3tmp2 r/w 28h (40 o c) the 3rd boundary temperature fo r vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 3 register (index bch). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 4 register (index bdh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt2 boundary 4 temperature ? index b9 bit name r/w default description 7-0 bound4tmp2 r/w 1eh (30 o c) the 4th boundary temperature fo r vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expected value will load from segment 4 register (index bdh). when vt2 temperature is below this boundary ? hysteresis, fan2 expected value will load from segment 5 register (index beh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. fan2 segment 1 speed count ? index bah bit name r/w default description 7 - 0 sec1speed2 r / w ffh (100%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expected fan speed % of the full speed in this temperature section. ex: 100%: full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ( (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
sep, 2011 v0.21p -54- F71889A fan2 segment 2 speed count ? index bbh bit name r/w default description 7-0 sec2speed2 r/w d9h (85%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 3 speed count ? index bch bit name r/w default description 7-0 sec3speed2 r/w b2h (70%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 4 speed count ? index bdh bit name r/w default description 7-0 sec4speed2 r/w 99h (60%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 segment 5 speed count ? index beh bit name r/w default description 7-0 sec5speed2 r/w 80h (50%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan2 temperature mapping select ? index bfh bit name r/w default description 7 fan2_temp_sel _dig r/w 0 this bit companying with fan2_temp_sel select the temperature source for controlling fan2. 6 reserved -- 0 reserved 5 fan2_up_t_en r / w 0 set 1 to force fan2 to full speed if any temperature over its high limit. 4 fan2_interpolation_ en r/w 0 set 1 will enable the interpol ation of the fan expect table. 3 fan2_jump_high_en r / w 0 this register controls the fan2 dut y movement when temperature over highest boundary. 0: the fan2 duty will increases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec1speed2 register. this bit only activates in duty mode. 2 fan2_jump_low_en r/w 0 this register controls the fan2 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan2 duty will decreases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec2speed2 register. this bit only activates in duty mode.
sep, 2011 v0.21p -55- F71889A 1-0 fan2_temp_sel r/w 1 this registers companying with fan2_temp_sel_dig select the temperature source for controlling fan2. the following value is comprised by {fan2_temp_sel_dig, fan2_temp_sel} 000: fan2 follows peci temperature (cr78h) 001: fan2 follows temperature 1 (cr72h). 010: fan2 follows temperature 2 (cr74h). 011: fan2 follows temperature 3 (cr76h). 100: fan2 follows amd tsi or intel ibx temperature (cr79h) 101: fan2 follows digital temperature 1 (cr7ch). 110: fan2 follows digital temperature 2 (cr7bh). 111: fan2 follows digital temperature 3 (cr7ah). otherwise: reserved. fan3 index c0h- cfh address attribute default value description c0h ro 8?h0f fan3 count reading (msb). at the moment of reading th is register, the lsb will be latched. this will prevent from dat a updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 8?hff fan3 count reading (lsb). c2h r/w 8?h00 rpm mode (cr96 bit4=0): fan3 expect speed count value (msb), in auto fan mode (cr96 bit5 ? 0) this register is auto updated by hardware. duty mode (cr96 bit4=1): this byte is reserved byte. c3h r/w 8?h01 rpm mode (cr96 bit4=0): fan3 expected speed count value (lsb) or expected pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode (cr96 bit4=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 8?h03 fan3 full speed count reading (msb). at t he moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 8?hff fan3 full speed count reading (lsb). vt3 boundary 1 temperature ? index c6h bit name r/w default description 7-0 bound1tmp3 r/w 3ch (60 o c) the 1st boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 1 register (index cah). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 2 register (index cbh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?.
sep, 2011 v0.21p -56- F71889A vt3 boundary 2 temperature ? index c7 bit name r/w default description 7-0 bound2tmp3 r/w 32 (50 o c) the 2nd boundary temperature for vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 2 register (index cbh). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 3 register (index cch). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt3 boundary 3 temperature ? index c8h bit name r/w default description 7-0 bound3tmp3 r/w 28h (40 o c) the 3rd boundary temperature fo r vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 3 register (index cch). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 4 register (index cdh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. vt3 boundary 4 temperature ? index c9 bit name r/w default description 7-0 bound4tmp3 r/w 1eh (30 o c) the 4th boundary temperature fo r vt3 in temperature mode. when vt3 temperature is exceed this boundary, fan3 expected value will load from segment 4 register (index cdh). when vt3 temperature is below this boundary ? hysteresis, fan3 expected value will load from segment 5 register (index ceh). this byte is a 2?s complement value ranging from -128 o c ~ 127 o c. bit 7 will always be ?0? (always positive) if fan_neg_temp_en is ?0?. fan3 segment 1 speed count ? index cah bit name r/w default description 7 - 0 sec1speed3 r / w ffh (100%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%: full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 2 speed count ? index cbh bit name r/w default description 7 - 0 sec2speed3 r / w d9h (85%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expected fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte means the expected pwm duty-cycle in this temperature section.
sep, 2011 v0.21p -57- F71889A fan3 segment 3 speed count ? index cch bit name r/w default description 7 - 0 sec3speed3 r / w b2h (70%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 4 speed count ? index cdh bit name r/w default description 7 - 0 sec4speed3 r / w 99h (60%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 segment 5 speed count ? index ceh bit name r/w default description 7 - 0 sec5speed3 r / w 80h (50%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. fan3 temperature mapping select ? index cfh bit name r/w default description 7 fan3_temp_sel _dig r/w 0 this bit companying with fan3_temp_sel select the temperature source for controlling fan3. 6 reserved -- 0 reserved 5 fan3_up_t_en r / w 0 set 1 to force fan3 to full speed if any temperature over its high limit. 4 fan3_interpolation_ en r/w 0 set 1 will enable the interpol ation of the fan expect table. 3 fan3_jump_high_en r / w 0 this register controls the fan3 dut y movement when temperature over highest boundary. 0: the fan3 duty will increases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec1speed3 register. this bit only activates in duty mode. 2 fan3_jump_low_en r/w 0 this register controls the fan3 dut y movement when temperature under (highest boundary ? hysteresis). 0: the fan3 duty will decreases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec2speed3 register. this bit only activates in duty mode.
sep, 2011 v0.21p -58- F71889A 1-0 fan3_temp_sel r/w 1 this registers companying with fan3_temp_sel_dig select the temperature source for controlling fan3. the following value is comprised by {fan3_temp_sel_dig, fan3_temp_sel} 000: fan3 follows peci temperature (cr78h) 001: fan3 follows temperature 1 (cr72h). 010: fan3 follows temperature 2 (cr74h). 011: fan3 follows temperature 3 (cr76h). 100: fan3 follows amd tsi or intel ibx temperature (cr79h) 101: fan3 follows digital temperature 1 (cr7ch). 110: fan3 follows digital temperature 2 (cr7bh). 111: fan3 follows digital temperature 3 (cr7ah). otherwise: reserved. tsi temperature 0 ? index e0h bit name r/w default description 7-0 tsi_temp0 r/w 8?h00 this byte is used as multi-purpose as follows: 1. amd tsi reading if amd tsi enable (0~255 o c). 2. highest temperature among cpu, mch and pch if intel ibx enable (0~255 o c). 3. the 1 st byte of read block prot ocol. to access this byte, mch_bank_sel must set to ?0?. smb_data0 r/w 8?h00 this byte is used as multi-purpose: 1. the received data of receive protocol. 2. the first received byte of read word protocol. 3. the 10th received byte of read block protocol. 4. the sent data for send byte pr otocol and write byte protocol. 5. the first send byte for write word protocol. 6. the first send byte for write block protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 1 ? index e1h bit name r/w default description 7-0 tsi_temp1 r 8?h00 this byte is used as multi-purpose as follows: 1. the pch temperature reading (0~255 o c). this byte is only valid if intel ibx is enabled. 2. the 2 nd byte of read block protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data1 r/w 8?h00 this byte is used as multi-purpose: 1. the second received byte of read word protocol. 2. the 11th received byte of read block protocol. 3. the second send byte for write word protocol. 4. the second send byte for write block protocol. to access this byte, mch_bank _sel should be set to ?1?.
sep, 2011 v0.21p -59- F71889A tsi temperature 2 low byte ? index e2h bit name r/w default description 7-0 tsi_temp2_lo r 8?h00 this byte is used as multi-purpose as follows: 1. the low byte of intel temperature interface cpu reading. the reading is the fraction part of cpu temper ature. bit 0 indicates the error status. logic ?1? indicates an error code. this byte is only valid if intel ibx is enabled. 2. the 3 rd byte of the block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data2 r/w 8?h00 this is the 12th byte of the block read protocol. this byte is also used as the 3rd byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 2 high byte ? index e3h bit name r/w default description 7-0 tsi_temp2_hi r 8?h00 this byte is used as multi-purpose as follows: 1. the high byte of intel temperature interface cpu reading. the reading is the decimal part of cpu temperature. this byte is only valid if intel ibx is enabled. 2. the 4 th byte of the block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data3 r/w 8?h00 this is the 13th byte of the block read protocol. this byte is also used as the 4th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 3 ? index e4h bit name r/w default description 7-0 tsi_temp3 r 8?h00 this byte is used as multi-purpose as follows: 1. the mch temperature reading (0~255 o c). this byte is only valid if intel ibx is enabled. 2. the 5 th byte of the block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data4 r/w 8?h00 this is the 14th byte of the block read protocol. this byte is also used as the 5th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?.
sep, 2011 v0.21p -60- F71889A tsi temperature 4 ? index e5h bit name r/w default description 7-0 tsi_temp4 r 8?h00 this byte is used as multi-purpose as follows: 1. the dimm0 temperature reading (0~255 o c). this byte is only valid if intel ibx is enabled. 2. the 6 th byte of the block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data5 r/w 8?h00 this is the 15th byte of the block read protocol. this byte is also used as the 6th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 5 ? index e6h bit name r/w default description 7-0 tsi_temp5 r 8?h00 this byte is used as multi-purpose: 1. the dimm1 temperature reading (0~255 o c). this byte is only valid if intel ibx is enabled. 2. the 7 th byte of the block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data6 r/w 8?h00 this is the 16th byte of the block read protocol. this byte is also used as the 7th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 6 ? index e7h bit name r/w default description 7-0 tsi_temp6 r 8?h00 this byte is used as multi-purpose as follows: 1. the dimm2 temperature reading (0~255 o c). this byte is only valid if intel ibx is enabled. 2. the 8 th byte of the block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data7 r/w 8?h00 this is the 17th byte of the block read protocol. this byte is also used as the 8th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. tsi temperature 7 ? index e8h bit name r/w default description 7-0 tsi_temp7 r 8?h00 this byte is used as multi-purpose: 1. the dimm3 temperature reading (0~255 o c). the byte is only valid if intel ibx is enabled. 2. the 9 th byte of block read protocol. to access this byte, mch_bank _sel should be set to ?0?. smb_data8 r/w 8?h00 this is the 18th byte of the block read protocol. this byte is also used as the 9th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?.
sep, 2011 v0.21p -61- F71889A smb data buffer 9 ? index e9h (mch_bank_sel = 1) bit name r/w default description 7-0 smb_data9 r/w 0 this is the 19 th byte of the block read protocol. this byte is also used as the 10th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. smb data buffer 10 ? index eah (mch_bank_sel = 1) bit name r/w default description 7-0 smb_data10 r/w 0 this is the 20 th byte of the block read protocol. this byte is also used as the 11th byte of block write protocol. to access this byte, mch_bank _sel should be set to ?1?. block write count register ? index ech bit name r/w default description 7 mch_bank_sel r/w 0 this bit is used to select the register in index e0h to e9h. set ?0? to read the temperature bank and ?1? to access the data bank. 6 reserved - 0 reserved 5-0 block_wr_cnt r/w 0 use the register to specify the byte c ount of block write protocol. support up to 10 bytes. smb command byte/tsi comamdn byte ? index edh (tsi_cmd_prog = 0) bit name r/w default description 7-0 smb_cmd r/w 8?h0 command code for write byte/word, read byte/word, block write/read and process call protocol. smb command byte/tsi comamdn byte ? index edh (tsi_cmd_prog = 1) bit name r/w default description 7-0 tsi_cmd r/w 8?h1 the command code for intel temperature interface block read protocol and the data byte for amd tsi send byte protocol. smb status ? index eeh bit name r/w default description 7 tsi_pending r/w 0 set 1 to pending auto tsi accessing. (in amd model, auto accessing will issue a send-byte followed a receive-byte; in intel model, auto accessing will issue a block read). to use the tsi_scl/tsi_sda as a smbus master, set this bit to ?1? first. 6 tsi_cmd_prog r/w 0 set 1 to program tsi_cmd. 5 proc_kill r/w 0 kill the current smbus transfer and return the state machine to idle. it will set a fail status if the current transfer is not completed. 4 fail_sts r 0 this is set when proc_ki ll kill an un-completed transfer. it will be auto cleared by next smbus transfer.
sep, 2011 v0.21p -62- F71889A 3 smb_abt_err r 0 this is the arbitration lost status if a smbus command is issued. auto cleared by next smbus command. 2 smb_to_err r 0 this is the timeout status if a sm bus command is issued. auto cleared by next smbus command. 1 smb_nac_err r 0 this is the nack error status if a smbus command is issued. auto cleared by next smbus command. 0 smb_ready r 1 0: smbus transfer is in process. 1: ready for next smbus command. smb protocol select ? index efh bit name r/w default description 7 smb_start w 0 write ?1? to trigger a smbus transfe r with the protocol specified by smb_protocol. 6-4 reserved - - reserved. 3-0 smb_protocol r/w 0 select what protocol if smbus transfer is triggered. 0001b: send byte. 0010b: write byte. 0011b: write word. 0100b: process call. 0101b: block write. 0111b: quick command (write). 1001b: receive byte. 1010b: read byte. 1011b: read word. 1101b: block read. 1111b: quick comm and (read). otherwise: reserved. 7.3.5 hw chip id and vender id information hm chip id 1 register ? index 5ah bit name r/w default description 7-0 hm_chip_id1 r 03h chip id 1 of hm device. hm chip id 2 register ? index 5bh bit name r/w default description 7-0 hm_chip_id2 r 04h chip id 2 of hm device. hm vendor id 1 register ? index 5dh bit name r/w default description 7-0 hm_vendor_id1 r 19h vendor id 1 of hm device. hm vendor id 2 register ? index 5eh bit name r/w default description 7-0 hm_vendor_id2 r 34h vendor id 2 of hm device.
sep, 2011 v0.21p -63- F71889A 7.4. keyboard controller the kbc provides the functions included a keyboard and a ps/2 mouse, and can be used with ibm-compatible personal computers or ps/2-based systems. the contro ller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interr upt to the system when data are placed in its output buffer. the below content is about the kbc device register descriptions. all the registers are for software porting reference. status register the status register is an 8 bits register at i/o address 64h that provides information about the status of the kbc bit name r/w default description 7 parity error r 0 0:odd parity 1:even parity 6 time out r 0 0:no time out error 1:time out error 5 auxiliary device obf r 0 0: auxiliary output buffer empty 1: auxiliary output buffer full 4 inhinit r 0 0:keyboard is inhibited 1: keyboard is not inhibited 3 command/data r 0 0:data byte 1:command byte 2 system_flag r 0 this bit is set or clear by command byte of kbc 1 ibf r 0 0:input buffer empty 1: input buffer full 0 obf r 0 0:output buffer empty 1: output buffer full command register the internal kbc operation is controlled by the kbc command byte (kccb). the kccb resides in i/o address 64h that is read with a 20h command and written with a 60h command data. bit name r/w default description 7 reserved - - reserved 6 translate code r/w 1 0: pass un-translated scan code. 1: translate scan code to ibm pc standard. 5 disable auxiliary device r/w 0 1: disable auxiliary inhibit function. 4 disable keyboard r/w 0 1: disable keyboard inhibit function. 3 reserved - - reserved 2 system flag r/w 1 0: the system is executing post as a result of a cold boot. 1: the system is executing post as a result of a shutdown or warm boot.
sep, 2011 v0.21p -64- F71889A 1 enable auxiliary interrupt r/w 1 0: ao interrupt 1: a system interrupt is generated when a byte is placed in output buffer (irq12). 0 enable keyboard interrupt r/w 1 0:no interrupt 1: a system interrupt is generated when a byte is placed in output buffer (irq1). data register the data register is an 8 bits register at i/o address 60h. the kbc used the output buffer to send the scan code received from keyboard and data by te replay by command to the system. power on default <7:0> = 00000000 binary commands command function 20h read command byte 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test returns 055h if self test succeeds abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high. 8?h03: indicate keyboard data is low. 8?h04: indicate keyb oard data is high. adh disable keyboard interface
sep, 2011 v0.21p -65- F71889A aeh enable keyboard interface c0h read input port (p1) and send data to the system c1h continuously puts the lower four bits of port1 into status register c2h continuously puts the upper four bits of port1 into status register cah read the data written by cbh command. cbh written a scratch data. this byte could be read by cah command. d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh pulse only rc (the reset line) low for 6 s if command byte is even kbc command description ps2 wakeup function the kbc supports keyboard and mouse wakeup function, keyboard wakeup function has 8 kinds of conditions, when key is pressed combinational key (1) ctrl +esc (2) ctrl+f1 (3) ctrl+space (4) any key (5) windows 98 wakeup up key (6) windows 98 power key (7) ctrl + alt + backspace (8) ctrl + alt + space. mouse wakeup function has 2 kinds of conditions, when mouse is pressed via (1) button clicking or (2) butt on clicking and movement, kb/mo will assert pme signal. those wakeup conditions are c ontrolled by the configuration register. 7.5. 80 port monitor the value of 0x80 port and output the val ue via the signals defined for 7-segment display. high nibble and low nibble are output interleaved at 1khz frequency. 7.6. acpi function the advanced configuration and power interface (acpi) is a system for c ontrolling the use of power in a computer. it lets computer manufacturer an d user to determine the computer?s power usage dynamically. there are three acpi states that are of primar y concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; t he computer is being actively used in this state. the other two are called sleep states and reflect differen t power consumption when pow er-down. s3 is a state that the processor is powered down but the last procedural state is bei ng stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, since me mory is fast, the computer can quickly come back to full-power state, the disk is slower than the memo ry and the computer takes longer time to come back to
sep, 2011 v0.21p -66- F71889A full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s3 s5 is illegal transition and won?t be allowed by state machine. it is necessary to enter s0 first in order to get to s5 from s3. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one register will keep the status of before power loss. if it is power on before power loss, it will remain power on when power is resum ed (system would send the psout# automatically), otherwise, if it is power off before power loss, it w ill remain power of f when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# 3vcc figure 18 default timing: always off
sep, 2011 v0.21p -67- F71889A vbat vsb rsmrst# s3# ps_on# psin# psout# 3vcc figure 19 optional timing: always on pci reset and pwrok signals the F71889A supports 3 output buffers for 3 reset signals. the result of pcirst# outcome will be affected by conditions as below: pcirst1# ? output buffer of lreset#. pcirst2# ? output buffer of lreset#. pcirst3# ? output buffer of lreset#. delay +3.3v atxpg lreset# pcirst1~3# pwrok
sep, 2011 v0.21p -68- F71889A so far as the pwrok issue is as the figure above. pwrok is delayed 100ms (default) as 3vcc arrives 2.8v, and the delay timing can be programmed by register. (100ms ~ 400ms) the F71889A also supports 3 output voltages for vref1~3. the output is generated from dacs which is powered by trimmed 2.304v reference voltage. one lsb is 2.304v/256. below is the timing sequence between vref1~3 pins: figure 20 vref timing: s5 ? s0
sep, 2011 v0.21p -69- F71889A figure 21 vref timing: s0 ? s3 figure 22 vref timing: s3 ? s0
sep, 2011 v0.21p -70- F71889A figure 23 vref timing: s0 ? s5 figure 24 vccgate & usben timing s0 s5 s3 deep s3 s0 s5 vcc vin3 (5vcc) vccgate 1 usben delay 100ms delay 100ms rsmrst# s3# (de-bounce 10us) s5# (de-bounce 10us)
sep, 2011 v0.21p -71- F71889A figure 25 susc# timing 7.7. peci function the platform environment control interface (peci) uses a single wire for self-clocking and data transfer. the bus requires no additional cont rol lines. the physical layer is a self-clocked on-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. the duration of the signal driven high depends on whether the bit value is a logic ?0? or login ?1?. peci also includes variable data transfer rate established with every message. in this way, it is highly flexible even though underlying logic is simple. the interface design was optimized for interfacing to intel processor and chipset components in both single processor and multiple processor environments. the single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to tr ansfer critical device operating conditions and configuration information. F71889A can connect to cpu & read the temperature data from cpu directly. then the fan control machine of F71889A can implement the fan to cool down cpu temperature. the application circuit is as below. peci F71889A cpu peci intel 100k avoid pre-bios floating intel peci typical application
sep, 2011 v0.21p -72- F71889A the F71889A integrated most of peci 3.0 commands for the future advantage application. more detail, please refer to the register descriptions. F71889A support peci 3.0 command name peci 1.0 command name status v ping( ) ping( ) v gettemp( ) gettemp( ) v getdib( ) v rdiamsr( ) - wriamsr( ) - rdpciconfiglocal( ) not available in mobile/dt - wrpciconfiglocal( ) not available in mobile/dt - rdpciconfig( ) not available in mobile/dt - wrpciconfig( ) not available in mobile/dt v rdpkgconfig( ) v wrpkgconfig( ) 7.8. sst function the simple serial transfer (sst) temperature sensor provides a mean to digitize an analog signal and send that information over a digital bus enabling remote temperature sensing in areas previously not monitored in the pc. the temperature sensor supports an internal and external thermal diode. the simple serial transfer (sst) interface provides sensed temperatures and voltages. the sensed temperatures are t1, t2, and t3 whose reading values stored in cr72h, cr74h, and cr76h. the sensed voltages are v1~v6 whose reading values stored in cr21h~26h. 7.9. tsi function the temperature sensor interface (tsi) was a simple smbus master to communicate with amd cpu or intel cpu to getting the temperature of cpu. it supports byte sending, byte reveiving, read/write byte, read/write block and quick command of smbus protocol. when power on the hardware automatically fetch the temperature use the protocol per the specification of amd/intel. user can use the provided registers to control the scl/sda as a smbus master. for intel platform, the smbus supports next generational ibx protocol for temperature reading. 7.10. power saving function erp power saving function erp_ctrl0#, erp_ctrl1#, and erp_ctrl2# control the standby power rail on/off to fulfill the purpose to decrease the power consumption w hen the system is under the sleep state or the soft-off state. those three pins are connected to the external pmoss with the default high in the
sep, 2011 v0.21p -73- F71889A sleep state in order to cut off all the standby power rails to save the power consumption. if the system needs to support wake-up function, those three pins can be programmable to set which power rail is needed to be turned on. the programmable register is powered by battery. so, the setting will be kept even the ac power is lost after the register is set. at the power saving state (fintek calls it g3-like state), the F71889A consumes 5vsb power rail only to realize a low power consumption system. F71889A su pports wake up events via event_in0#, event_in1#, kb/mo & cir function from s3/s5 state. intel cougar point timing (cpt) the F71889A supports intel cougar point chipset (cpt) timing for sandy bridge platform. there are 4 pins for cpt control: sus_warn#, sus_ack#, slp_sus# and dpwrok. for entering intel deep sleep well (dsw) state, the pch will assert sus_warn# and turn off 5vdual. after the level of 5vdual is lower than 1.05v, F71889A will assert sus_ack# to inform pch to ready for entering dsw. finally, pch will ramp down the internal vccsus and assert slp_sus# to F71889A. F71889A will turn off the 5vsb and 3vsb by erp_ctrl0# and enter the dsw state. to exit dsw state, pch will de-assert slp_sus#, turn on the sus rail fets and ramp up internal 1.05v vccsus. after the sus rails voltages are up, rsmrst# will be desserted and the pch will release sus_warn# so that the 5vdual will ramp up. because the dsw function is controlled by F71889A instead of controlled by pch directly, there will be more wakeup events such as lan, kb/mouse, sio ri# wake up rather than the 3 wakeup events (rtc, power button and gpio27) for intel dsw. in order to achieve lower power consumption, F71889A provides the erp_ctrl1# to turn off the v3a so that the system can enter the fintek g3? state. if it?s required to provide wake on lan (wol) or other wake on devices functions, F71889A also support one extra erp_ctrl2# pin to realize this function. the block diagram below shows how the connection and control method for F71889A and pch.
sep, 2011 v0.21p -74- F71889A 7.11. cir function the F71889A is compatible with microsoft windows vista and windows 7 ir receiver or transceiver emulation device which supports rc6 & qp protocol. it supports 1 ir transceiver functions for blaster application and 1 ir receiver with long range frequency and another with wide band application. the wide-band receiver is necessary to support ir learning, ir-blasting and set-top box control. the long-range receiver is a receiver which has the following characteristics: 1. works at a distance of 10 meters. 2. demodulates the signal inside the receiver part 3. has a bpf which works with carriers from 32-60 khz. the wide-band receiver is a receiver part which has the following characters: 1. works at a distance of approximately 5 centimeters. 2. does not demodulate the signal inside the receiver part 3. works with carriers from 32-60 khz (probably doesn?t have a bpf, but still has the same or wider range). in power function, the F71889A supports vista and windows 7 wakeup programming function when the pc is in the s3 state. the F71889A decodes ir protocol via the same vista and windows 7 s0 state s3 state s4/s5 dsw g3? g3 atx power 5vsb vcc 5vdual 3.3v vsb vr v5a erp_ctrl0# (slp_sus_fet) 5vsb 3vsb v3a cpt pch F71889A sus_warn# sus_ack# slp_sus# 5va_pwok# rsmrst# v3a v5a 3vsb dpwrok rsmrst# 5vdual sus_warn# mb logic 5vdual control erp_ctrl1# sus_warn erp_ctrl0# erp_ctrl1# v detect & delay (invert from pch) suswarn# susack# i_3vsb erp_ctrl2# la wol 1.05v
sep, 2011 v0.21p -75- F71889A wakeup programming key. the F71889A is asserted pme or psout to wakeup pc system.the wake up programming function is reference from microsoft vista and windows 7 remote controller specification. please reference microsoft windows vista / 7 ir rece iver or transceiver emulation device spec. for further detail. 7.12. scan code function F71889A three gpio pins, gpio 50/51/52, can emulate kbc command and then assert make/break scan code. those pins can not only be set to volume up/down, and mute but also any function keys on keyboard. because the protocol for those pins is scan code, so it doesn?t require a driver to connect this function to os. if the button for the gpio has been pressed continuesly over nearly 1 second (delay time), the gpio will repeatedly sending this function in an interval of 50 ms (repeat time). the delay time could be set from 0.5 to 1 sec (unit: 0.5s).
sep, 2011 v0.21p -76- F71889A 8 register description the configuration register is used to control the behavior of the corresponding devices. to configure the register, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. pull down the sout1 pin to change the default value to 0x2e/0x2f. to enable configuration, the entry key 0x87 must be written to the index port. to disable configuration, write exit key 0xaa to the index port. following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 (enable configuration) -o 4e aa (disable configuration) the following is a register map (total devic es) grouped in hexadecimal address order, which shows a summary of all registers and their default value. please refer each device chapter if you want more detail information. ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 02 software reset register 0 - - - - - - 0 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20 chip id register 0 0 0 1 0 0 0 0 21 chip id register 0 0 0 0 0 1 0 1 23 vender id register 0 0 0 1 1 0 0 1 24 vender id register 0 0 1 1 0 1 0 0 25 software power down register - - - 0 0 0 0 0 26 uart irq sharing register 0 - 0 - - 0 0 0 27 configuration port select register 1/0 - - 1/0 - - 1/0 1/0 28 80 port enable register - 0 0/1 0 - - - - 29 multi function select 4 register 0 0 0 0 0 0 0 0 2a multi function select 1 register 1 1 1 1 0 0 0 0 2b multi function select 2 register 0 0 1 1 0 0 0 0 2c multi function select 3 register 0 0 0 1 0 0 0 0 2d wakeup control register 0 0 0 0 1 0 0 0 ?-? reserved or tri-state uart1 device configuration registers (ldn cr01) register 0x[hex] register name default value msb lsb 30 uart1 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 1 0 0 0
sep, 2011 v0.21p -77- F71889A 70 irq channel select register - - - - 0 1 0 0 f0 rs485 enable register - - - 0 - - - - uart2 device configuration registers (ldn cr02) register 0x[hex] register name default value msb lsb 30 uart2 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 rs485 enable register - - - 0 0 0 - - f1 sir mode control register - - - 0 0 1 0 0 parallel port device config uration registers (ldn cr03) register 0x[hex] register name default value msb lsb 30 parallel port device en able register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 0 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 1 1 74 dma channel select register - - - 0 - 0 1 1 f0 prt mode select register 0 1 0 0 0 0 1 0 hardware monitor device conf iguration registers (ldn cr04) register 0x[hex] register name default value msb lsb 30 h/w monitor device enabl e register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 kbc device configuration registers (ldn cr05) register 0x[hex] register name default value msb lsb 30 kbc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 70 kb irq channel select register - - - - 0 0 0 1 72 mouse irq channel select register - - - - 1 1 0 0 fe auto swap register 1 - - 0 0 0 0 1 ff user wakeup code register 0 0 1 0 1 0 0 1 gpio device configuration registers (ldn cr06) register 0x[hex] register name default value msb lsb f0 gpio output enable register - 0 0 0 0 0 0 0 f1 gpio output data register - 1 1 1 1 1 1 1 f2 gpio pin status register - - - - - - - - f3 gpio drive enable register - 0 0 0 0 0 0 0 fe led_vsb control register - 0 0 0 0 0 0 0 ff led_vcc control register 0 0 0 0 0 0 0 0 e0 gpio1 output enable register - 0 0 0 0 0 0 0 e1 gpio1 output data register - 1 1 1 1 1 1 1 e2 gpio1 pin status register - - - - - - - - e3 gpio1 drive enable register - 0 0 0 0 0 0 0 d0 gpio2 output enable register 0 0 0 - - - - - d1 gpio2 output data register 1 1 1 - - - - - d2 gpio2 pin status register - - - - - - - -
sep, 2011 v0.21p -78- F71889A d3 gpio2 drive enable register 0 0 0 - - - - - c0 gpio3 output enable register 0 0 0 0 0 0 0 0 c1 gpio3 output data register 1 1 1 1 1 1 1 1 c2 gpio3 pin status register - - - - - - - - c3 gpio3 drive enable register 0 0 0 0 0 0 0 0 b0 gpio4 output enable register 0 0 0 0 0 0 0 0 b1 gpio4 output data register 1 1 1 1 1 1 1 1 b2 gpio4 pin status register - - - - - - - - a0 gpio5 output enable register - - - 0 0 0 0 0 a1 gpio5 output data register - - - 1 1 1 1 1 a2 gpio5 pin status register - - - - - - - - a4 gpio5 pme enable register - - - 0 0 0 0 0 a5 gpio5 input event detection se lect register - - - 0 0 0 0 0 a6 gpio5 event status register - - - 0 0 0 0 0 ab gpio52 kbc emulation make code register 0 0 0 0 0 0 0 0 ac gpio51 kbc emulation make code register 0 0 0 0 0 0 0 0 ad gpio50 kbc emulation make code register 0 0 0 0 0 0 0 0 ae gpio5 kbc emulation prefix code register 1 1 1 0 0 0 0 0 af gpio5 kbc emulation control register 0 0 0 0 0 0 0 0 90 gpio6 output enable register 0 0 0 0 0 0 0 0 91 gpio6 output data register 1 1 1 1 1 1 1 1 92 gpio6 pin status register - - - - - - - - 93 gpio6 drive enable register 0 0 0 0 0 0 0 0 80 gpio7 output enable register 0 0 0 0 0 0 0 0 81 gpio7 output data register 1 1 1 1 1 1 1 1 82 gpio7 pin status register - - - - - - - - 83 gpio7 drive enable register 0 0 0 0 0 0 0 0 vid device configuration registers (ldn cr07) register 0x[hex] register name default value msb lsb 30 vid device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 f0 watchdog timer configuration register 1 0 - - - - - - 0 f2 bus manual register 0 - 0 0 0 0 0 0 f3 key data register 0 0 0 0 0 0 0 0 f4 busin status register 0 0 0 0 0 - - - f5 wdt (watchdog timer) configuration register 2 - 0 0 0 0 0 0 0 f6 wdt (watchdog timer) configuration register 3 0 0 0 0 0 0 0 0 f7 nb offset register 0 0 0 0 0 0 0 0 f8 vdd0 offset register 0 0 0 0 0 0 0 0 f9 vdd1 offset register 0 0 0 0 0 0 0 0 fa watchdog timer pme register 0 0 0 0 0 0 0 0 fb vdd nb manaul register 0 0 0 0 0 0 0 0 fc vdd0 manaul register 0 0 0 0 0 0 0 0 fd vdd1 manaul register 0 0 0 0 0 0 0 0 fe psi control register 0 0 0 0 1 1 1 0 cir device configuration registers (ldn cr08) register 0x[hex] register name default value msb lsb 30 cir device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0
sep, 2011 v0.21p -79- F71889A 61 base address low register 0 0 0 0 0 0 0 0 70 cir irq channel select register - - - - 0 0 0 0 f0 reserved - - - - - - - - f1 reserved - - - - - - - - f8 reserved 0 0 0 0 0 0 0 0 f9 reserved 0 0 0 0 0 0 0 0 fa reserved 1 0 0 0 0 0 0 0 fb reserved 0 0 1 1 1 0 1 1 fc reserved 0 0 0 0 0 0 0 0 fd reserved 0 0 0 0 0 0 0 0 fe reserved 0 0 0 0 0 0 0 0 pme, acpi and erp device configuration registers (ldn cr0a) register 0x[hex] register name default value msb lsb 30 pme device enable register - - - - - - - 0 f0 pme event enable 1 register - 0 0 0 0 0 0 0 f1 pme event status 1 register - - - - - - - - f2 pme event enable 2 register - - - 0 - 0 0 0 f3 pme event status 2 register - - - - - - - - f4 acpi control register1 0 0 1 0 0 1 1 0 f5 acpi control register2 0 0 0 0 0 1 0 0 f6 acpi control register3 0 - 0 0 0 1 1 1 f7 acpi control register 4 0 0 - 1 - - 0 0 fa led mode select register - 0 0 0 - 0 0 0 fc intel dsw delay register - - - 0 0 0 0 0 fd trim data register (fintek test mode) - - - 0 - 0 0 0 fe ri de-bounce select register - - - 0 - - 0 0 e0 erp enable register 1 0 - - 0 0 0 0 e1 erp control register 1 1 1 0 0 1 1 0 0 e2 erp control register 2 - - 0 0 1 1 0 0 e3 erp psin deb-register 0 0 0 1 0 0 1 1 e4 erp rsmrst deb-register 0 0 0 0 1 0 0 1 e5 erp psout deb-register 1 1 0 0 0 1 1 1 e6 erp pson deb-register 0 0 0 0 1 0 0 1 e7 erp s5 deb-register 0 1 1 0 0 0 1 1 e8 erp wakeup event enable register 0 - 0 1 - 0 0 0 e9 erp deep s3 delay register 0 0 0 0 1 1 1 1 ec erp control register 3 0 0 0 0 1 0 1 0 ed erp watchdog control register - - - 0 - - 0 0 ee erp watchdog time register 0 0 0 0 0 0 0 0 vref control device configuration registers (ldn cr0b) register 0x[hex] register name default value msb lsb f0 vref3 output value 0 1 1 0 0 1 0 0 f1 vref2output value 0 1 1 0 0 1 0 0 f2 vref1 output value 0 1 1 0 0 1 0 0 f3 voltage lsb - - - - - 0 0 0 ff wdt reset enable - - - - - - - 0
sep, 2011 v0.21p -80- F71889A 8.1 global control registers 8.1.1 software reset register ? index 02h bit name r/w default description 7 temp_update_rate r/w 0 0: digital interface (peci/tsi/ibx) transmits when every temperature updates 1: digital interface (peci/tsi/ibx) transmits when every four times temperature updates 6-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the r egister and device powered by vdd (3vcc). 8.1.2 logic device number register (ldn) ? index 07h bit name r/w default description 7-0 ldn r/w 00h 00h: reserved. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor device configuration registers. 05h: select kbc device c onfiguration registers. 06h: select gpio device c onfiguration registers. 07h: select vid device c onfiguration registers. 07h: cir device config uration registers. 0ah: select pme, acpi & erp dev ice configuration registers. 0bh: select vref control dev ice configuration registers. 8.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 10h chip id1. 8.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 05h chip id2. 8.1.5 vendor id register ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id1 of fintek devices. 8.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id2 of fintek devices. 8.1.7 software power down register ? index 25h bit name r/w default description 7-5 reserved - - reserved
sep, 2011 v0.21p -81- F71889A 4 softpd_hm r/w 0 power down the hardware monitor device. this will stop the hardware monitor clock. 3 softpd_prt r/w 0 power down the parallel port device. this will stop the parallel port clock. 2 softpd_ur2 r/w 0 power down the uart 2 device. this will stop the uart 2 clock. 1 softpd_ur1 r/w 0 power down the uart 1 device. this will stop the uart 1 clock. 0 softpd_fdc r/w 0 power down the fdc device. this will stop the fdc clock. 8.1.8 uart irq sharing register ? index 26h bit name r/w default description 7 clk24m_sel r/w 0 0: clkin is 48mhz 1: clkin is 24mhz 6 reserved - - reserved. 5 dport_dec_sel r/w 0 0: the 80 port address is decoded as 0x0080. 1: the 80 port address is decoded as the scr of uart2. this bit is powered by vbat. 4-3 reserved - - reserved. 2 tx_del_1bit r/w 0 0: uart tx transmits data immediately after write thr. 1: uart tx transmits data delay 1 bit time after write thr. 1 irq_mode r/w 0 0: pci irq sharing mode (low level). 1: isa irq sharing mode (low pulse). 0 irq_shar r/w 0 0: disable irq sharing of two uart devices. 1: enable irq sharing of two uart devices. 8.1.9 rom address select register ? index 27h bit name r/w default description 7 ovp_mode r/w - 1: alarm mode voltage protection. voltag e protection is enabled by register. 0: force mode voltage protection. volt age protection is enabled after power on. the default value is determined by ovp_strap pin on power on. 6-5 reserved - - reserved. 4 port_4e_en r/w - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by sout1/ config4e_2e. pull down to select port 2e/2f. 3-2 reserved - - reserved. 1-0 lpt_func_sel r/w - 00: the parallel port pins function as lpt. 01: reserved. 10: the parallel port pins function as gpios.
sep, 2011 v0.21p -82- F71889A 8.1.10 80 port enable register ? index 28h bit name r/w default description 7 lpt_dport_en r/w - 0: the 80 port data could not be output to lpt pins. 1: the 80 port data could be output to lpt pins in dport_en is set to ?1?. 6 cir_led_gp40_en r/w 0 gpio40/cir_led# function select. the pin function is controlled by {cir_led_gp40_en, fdc_gp_en} 1x: the pin function is cir_led#. 01: the pin function is gpio 40. 00: reserved. 5 dport_en r/w - 0: the 80 port function is disabled. 1: the 80 port function is enabled. 4 temp_out_en r/w 0 set this bit to ?1? will output the cpu temperature to the 7-segment led. 3-0 reserved - - reserved. 8.1.11 multi function select 4 register ? index 29h (powered by vsb3v) bit name r/w default description 7 fdc_gp_rst_sel r/w 0 this bit selects the reset signal for gpio4 and gpio5. 0: reset by internal vsb5v power good. 1: reset by lreset#. 6 tsi_gp16_en r/w 0 peci/tsi_dat/ibx_dat/gpio16 function select. the pin function is controlled by {tsi_gp16_en, gpio16_en} 1x: the pin function is tsi_dat/ibx_dat. 01: the pin function is gpio16. 00: the pin function is peci. 5 tsi_gp15_en r/w 0 sst/tsi_clk/ibx_clk/gpio15 function select. the pin function is controlled by {tsi_gp15_en, gpio15_en} 1x: the pin function is tsi_clk/ibx_clk. 01: the pin function is gpio15. 00: the pin function is sst. 4 gpio14_lv_sel r/w 0 cirwb#/tsi_dat/ibx_dat/gpio14 input level select. 0: ttl input level. 1: low input level. 0.9v for high and 0.6v for low. 3 gpio13_lv_sel r/w 0 cirtx/tsi_clk/ibx_clk/gpio13 input level select. 0: ttl input level. 1: low input level. 0.9v for high and 0.6v for low. 2 gpio27_en r/w 0 sus_warn#/gpio27 function select. 0: the pin function is sus_warn#. 1: the pin function is gpio27. 1 gpio26_en r/w 0 slp_sus#/gpio26 function select. 0: the pin function is slp_sus#. 1: the pin function is gpio26.
sep, 2011 v0.21p -83- F71889A 0 gpio25_en r/w 0 cirrx#/gpio25 function select. 0: the pin function is cirrx#. 1: the pin function is gpio25. 8.1.12 multi function select 1 register ? index 2ah (powered by vsb3v) bit name r/w default description 7-6 gpio06_sel r/w 2?b11 susc#/gpio06/beep/alert# function select. 00: the pin function is alert#. 01: the pin function is beep. 10: the pin function is gpio06. 11: the pin function is susc#. 5 gpio05_en r/w 1 gpio05/led_vcc function select. 0: the pin function is led_vcc. 1: the pin function is gpio05. this bit is powered by vbat. 4 gpio04_en r/w 1 gpio04/led_vsb function select. 0: the pin function is led_vsb. 1: the pin function is gpio04. this bit is powered by vbat. 3 gpio03_sel r/w 0 slotocc#/gpio03 function select. 0: the pin function is slotocc#. 1: the pin function is gpio03. 2 gpio02_en r/w 0 dpwrok/gpio02 function select. 0: the pin function is dpwrok. 1: the pin function is gpio02. 1 gpio01_en r/w 0 sus_ack#/gpio01 function select. 0: the pin function is sus_ack#. 1: the pin function is gpio01. 0 gpio00_en r/w 0 erp_ctrl2#/gpio00 function select. 0: the pin function is erp_ctrl2#. 1: the pin function is gpio00. 8.1.13 multi function select 2 register ? index 2bh (powered by vsb3v) bit name r/w default description 7-6 gpio13_sel r/w 00b irtx/gpio13 function select. 00: reserved. 01: the pin function is irtx. 10: reserved. 11: the pin function is gpio13
sep, 2011 v0.21p -84- F71889A 5-4 gpio12_sel r/w 11b gpio12/wdtrst# function select. 00: the pin function is wdtrst#. 01: reserved. 10: the pin function is gpio12. 11: the pin function is cirled. 3-2 gpio11_sel r/w 00b fanctrl3/gpio11/irtx1 function select. 00: the pin function is fanctrl3. 01: the pin function is irtx1. 10: reserved. 11: the pin function is gpio11. 1-0 gpio10_sel r/w 00b fanin3/gpio10/irrx1 function select. 00: the pin function is fanin3. 01: the pin function is irrx1. 10: reserved. 11: the pin function is gpio10. 8.1.14 multi function select 3 register ? index 2ch (powered by vsb3v) bit name r/w default description 7 gpio1_2_rst_sel r/w 0 0: reset by internal vsb5v power good. 1: reset by lreset# 6 ur2_gp_en2 r/w 0 0: pin2~4 and pin126~128 function as uart2 modem control. 1: pin2~4 and pin126~128 function as gpio3x. 5 ur2_gp_en1 r/w 0 0: pin5, 6 function as uart2 sout2/sin2. 1: pin5, 6 function as gpio3x. 4 fdc_gp_en r/w 0 0: reserved. 1: pin 7 ~19 function as gpios. 3 gpio16_sel r/w 0 peci/tsi_dat/ibx_sda/gpio16 function select. 0: the pin function is peci/tsi_dat/ibx_sda decided by intel_model register. 1: the pin function is gpio16. 2 gpio15_sel r/w 0 sst/tsi_clk/ibx_clk/gpio15 function select. 0: the pin function is sst/tsi_clk/ibx_clk decided by intel_model register. 1: the pin function is gpio15. 1-0 gpio14_sel r/w 00b irrx/gpio14 function select. 00: reserved. 01: the pin function is irrx. 10: reserved. 11: the pin function is gpio14. 8.1.15 wakeup control register ? index 2dh (powered by vbat) bit name r/w default description 7 slot_pwr_sel r/w 0 0: slotocc# is pull-up to vsb3v. 1: slotocc# is pull-up to vbat.
sep, 2011 v0.21p -85- F71889A 6 vsbok_hys_dis r/w 0 0: rsmrst# will sink low when vsb3v is below 2.5v. 1: rsmrst# will sink low when vsb3v is below 2.8v. vsb3v power good level is 2.8v. 5 vref_s3 r/w 0 1: vref2 and 3 keep power on in s3 state 0: vref2 and 3 are power down in s3 state 4 key_sel_add r/w 0 this bit is added to add more wakeup key function. 3 wakeup_en r/w 1 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up. 2-1 key_sel r/w 00 this registers select the keyboard wake up key. accompanying with key_sel_add, there are eight wakeup keys: key_sel_add key_sel wakeup key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + space 0 11 any key 1 00 windows wakeup 1 01 windows power 1 10 ctrl + alt + space 1 11 space 0 mo_sel r/w 0 this register selects the mouse wake up key. 0: wake up by clicking. 1: wake up by clicking and movement. 8.2 uart1 registers (cr01) uart 1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur1_en r/w 1 0: disable uart 1. 1: enable uart 1. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 1 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 1 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur1irq r/w 4h select the irq channel for uart 1. rs485 enable register ? index f0h bit name r/w default description 7-6 reserved - - reserved.
sep, 2011 v0.21p -86- F71889A 5 rs485_inv r/w 0 0: normal rs485 mode. 1: rts# is inverted in rs485 mode. 4 rs485_en r/w 0 rs485 mode enable. 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low . 3-0 reserved - - reserved. 8.3 uart 2 registers (cr02) uart 2 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur2_en r/w 1 0: disable uart 2. 1: enable uart 2. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of uart 2 base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 2 base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur2irq r/w 3h select the irq channel for uart 2. rs485 enable register ? index f0h bit name r/w default description 7-6 reserved - - reserved. 5 rs485_inv r/w 0 0: normal rs485 mode. 1: rts# is inverted in rs485 mode. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. auto drive rts# high when transmitting data, otherwise is kept low. 3 rxw4c_ir r/w 0 0: no reception delay when sir is changed form tx to rx. 1: reception delays 4 characters time when sir is changed form tx to rx. 2 txw4c_ir r/w 0 0: no transmission delay when sir is changed form rx to tx. 1: transmission delays 4 characters time when sir is changed form rx to tx. 1-0 reserved - - reserved. sir mode control register ? index f1h bit name r/w default description 7-5 reserved - - reserved.
sep, 2011 v0.21p -87- F71889A 4-3 irmode r/w 00 00: disable ir function. 01: disable ir function. 10: irda function, active pulse is 1.6us. 11: irda function, active pulse is 3/16 bit time. 2 hduplx r/w 1 0: sir is in full duplex mode for loopbak test. txw4c_ir and rxw4c_ir are of no use. 1: sir is in half duplex mode. 1 txinv_ir r/w 0 0: irtx1 is in normal condition. 1: inverse the irtx1. 0 rxinv_ir r/w 0 0: irrx1is in normal condition. 1: inverse the irrx1. 8.4 parallel port registers (cr03) parallel port device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 prt_en r/w 1 0: disable parallel port. 1: enable parallel port. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of parallel port base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 78h the lsb of parallel port base address. irq channel select register ? index 70h bit name r/w default description 7-5 reserved - - reserved. 3-0 selprtirq r/w 7h select the irq channel for parallel port. dma channel select register ? index 74h bit name r/w default description 7-5 reserved - - reserved. 4 ecp_dma_mode r/w 0 0: non-burst mode dma. 1: enable burst mode dma. 3 reserved - - reserved. 2-0 selprtdma r/w 011 select the dma channel for parallel port. prt mode select register ? index f0h bit name r/w default description 7 spp_irq_mode r/w 0 interrupt mode in non-ecp mode. 0: level mode. 1: pulse mode. 6-3 ecp_fifo_thr r/w 1000 ecp fifo threshold.
sep, 2011 v0.21p -88- F71889A 2-0 prt_mode r/w 010 000: standard and bi-direction (spp) mode. 001: epp 1.9 and spp mode. 010: ecp mode (default). 011: ecp and epp 1.9 mode. 100: printer mode. 101: epp 1.7 and spp mode. 110: reserved. 111: ecp and epp1.7 mode. 8.5 hardware monitor registers (cr04) 8.6.1 hardware monitor configuration registers hardware monitor device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of hardware monitor base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hardware monitor base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selhmirq r/w 0000 select the ir q channel for hardware monitor. 8.6 kbc registers (cr05) kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc command port address. the address of data port is command port address + 4.
sep, 2011 v0.21p -89- F71889A base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc command port address. the address of data port is command port address + 4. kb irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selkirq r/w 1h select the irq channel for keyboard interrupt. mouse irq channel select register ? index 72h bit name r/w default description 7-4 reserved - - reserved. 3-0 selmirq r/w ch select the irq channel for ps/2 mouse interrupt. auto swap register ? index feh (powered by vbat) bit name r/w default description 7 auto_det_en r/w 1b 0: disable auto detect keyboard/mouse swap. 1: enable auto detect keyboard/mouse swap. 6-5 reserved - - reserved. 4 kb_mo_swap r/w 0b 0: keyboard/mouse does not swap. 1: keyboard/mouse swaps. this bit is set/clear by hardware if auto_det_en is set to ?1?. users could also program this bit manually. 3 pseudo_8408_en r/w 0 set ?1? to enable auto response to kbc command. it will return to 0xfa, 0xaa for 0xff command and 0xfa for ot her commands. this bit is used for gpio scan code function without ps/2 keyboard. 2-0 reserved r/w 1h reserved user wakeup code register ? index ffh (powered by vbat) bit name r/w default description 7-0 user_wakeup_co de r/w 29h this is the user defined code for wakeup function. 8.7 gpio registers (cr06) ( all registers of gpio are powered by vsb3v) gpio0 output enable register ? index f0h bit name r/w default description 7 reserved - - reserved. 6 gpio06_oe r/w 0 0: gpio06 is in input mode. 1: gpio06 is in output mode. 5 gpio05_oe r/w 0 0: gpio05 is in input mode. 1: gpio05 is in output mode. 4 gpio04_oe r/w 0 0: gpio04 is in input mode. 1: gpio04 is in output mode. 3 gpio03_oe r/w 0 0: gpio03 is in input mode. 1: gpio03 is in output mode.
sep, 2011 v0.21p -90- F71889A 2 gpio02_oe r/w 0 0: gpio02 is in input mode. 1: gpio02 is in output mode. 1 gpio01_oe r/w 0 0: gpio01 is in input mode. 1: gpio01 is in output mode. 0 gpio00_oe r/w 0 0: gpio00 is in input mode. 1: gpio00 is in output mode. gpio0 output data register ? index f1h bit name r/w default description 7 reserved - - reserved. 6 gpio06_val r/w 1 0: gpio06 outputs 0 when in output mode. 1: gpio06 outputs1 when in output mode. 5 gpio05_val r/w 1 0: gpio05 outputs 0 when in output mode. 1: gpio05 outputs 1 when in output mode. 4 gpio04_val r/w 1 0: gpio04 outputs 0 when in output mode. 1: gpio04 outputs 1 when in output mode. 3 gpio03_val r/w 1 0: gpio03 outputs 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 1 0: gpio02 outputs 0 when in output mode. 1: gpio02 outputs 1 when in output mode. 1 gpio01_val r/w 1 0: gpio01 outputs 0 when in output mode. 1: gpio01 outputs 1 when in output mode. 0 gpio00_val r/w 1 0: gpio00 outputs 0 when in output mode. 1: gpio00 outputs 1 when in output mode. gpio0 pin status register ? index f2h bit name r/w default description 7 reserved - - reserved. 6 gpio06_in r - the pin status of susc#/gpio06/beep/alert#. 5 gpio05_in r - the pin stat us of gpio05/led_vcc. 4 gpio04_in r - the pin st atus of gpio04/led_vsb. 3 gpio03_in r - the pin status of slotcc#/gpio03. 2 gpio02_in r - the pin stat us of dpwrok/gpio02. 1 gpio01_in r - the pin stat us of sus_ack#/gpio01. 0 gpio00_in r - the pin stat us of erp_ctrl2#/gpio00. gpio0 drive enable register ? index f3h bit name r/w default description 7 reserved - - reserved. 6 gpio06_drv_en r/w 0 0: gpio06 is open drain in output mode. 1: gpio06 is push pull in output mode. 5 gpio05_drv_en* r/w 0 0: gpio05 is open drain in output mode. 1: gpio05 is push pull in output mode. this bit is powered by vbat.
sep, 2011 v0.21p -91- F71889A 4 gpio04_drv_en* r/w 0 0: gpio04 is open drain in output mode. 1: gpio04 is push pull in output mode. this bit is powered by vbat. 3 gpio03_drv_en r/w 0 0: gpio03 is open drain in output mode. 1: reserved. 2 gpio02_drv_en r/w 0 0: gpio02 is open drain in output mode. 1: gpio02 is push pull in output mode. 1 gpio01_drv_en r/w 0 0: gpio01 is open drain in output mode. 1: gpio01 is push pull in output mode. 0 gpio00_drv_en r/w 0 0: gpio00 is open drain in output mode. 1: gpio00 is push pull in output mode. led_vsb control register ? index feh (powered by vbat) bit name r/w default description 7 reserved - - reserved. 6 led_vsb_ds3 r/w 0 set this bit ?1? to enable led_vsb deep s3 mode. led_vsb will output 0.25hz clock with 25% duty in deep s3 state. 5-4 led_vsb_s5_mode r/w 0 these bits control the led_v sb output mode in s5 state. the led_vsb output is controlled by {led_vsb_s5_add, led_vsb_s5_mode} 000: sink 0 001: tri-state. 010: 0.5hz clock 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty. 111: 0.25hz clock with 25% duty. 3-2 led_vsb_s3_mode r/w 0 these bits control the led_v sb output mode in s3 state. the led_vsb output is controlled by {led_vsb_s3_add, led_vsb_s3_mode} 000: sink 0 001: tri-state. 010: 0.5hz clock 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty. 111: 0.25hz clock with 25% duty.
sep, 2011 v0.21p -92- F71889A 1-0 led_vsb_s0_mode r/w 0 these bits control the led_v sb output mode in s0 state. the led_vsb output is controlled by {led_vsb_s0_add, led_vsb_s0_mode} 000: sink 0 001: tri-state. 010: 0.5hz clock 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty. 111: 0.25hz clock with 25% duty. led_vcc control register ? index ffh (powered by vbat) bit name r/w default description 7 led_vcc_inv_dis r/w 0 0: led_vcc output clock is inverted. 1: led_vcc output clock is not inverted. 6 led_vcc_ds3 r/w 0 set this bit ?1? to enable led_vcc deep s3 mode. led_vcc will output 0.25hz clock with 25% duty in deep s3 state. 5-4 led_vcc_s5_mode r/w 0 these bits control the led_vcc output mode in s5 state. the led_vcc output is controlled by {led_vcc_s5_add, led_vcc_s5_mode} 000: sink 0 001: tri-state. 010: 0.5hz clock 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty. 111: 0.25hz clock with 25% duty. 3-2 led_vcc_s3_mode r/w 0 these bits control the led_vcc output mode in s3 state. the led_vcc output is controlled by {led_vcc_s3_add, led_vcc_s3_mode} 000: sink 0 001: tri-state. 010: 0.5hz clock 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty. 111: 0.25hz clock with 25% duty.
sep, 2011 v0.21p -93- F71889A 1-0 led_vcc_s0_mode r/w 0 these bits control the led_vcc output mode in s0 state. the led_vcc output is controlled by {led_vcc_s0_add, led_vcc_s0_mode} 000: sink 0 001: tri-state. 010: 0.5hz clock 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 25% duty. 111: 0.25hz clock with 25% duty. gpio1 output enable register ? index e0h bit name r/w default description 7 reserved - - reserved. 6 gpio16_oe r/w 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 0 0: gpio15 is in input mode. 1: gpio15 is in output mode. 4 gpio14_oe r/w 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. gpio1 output data register ? index e1h bit name r/w default description 7 reserved - - reserved. 6 gpio16_val r/w 1 0: gpio16 outputs 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 1 0: gpio15 outputs 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 1 0: gpio14 outputs 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode.
sep, 2011 v0.21p -94- F71889A gpio1 pin status register ? index e2h bit name r/w default description 7 reserved - - reserved. 6 gpio16_in r - the pin status of peci/tsi_dat/ibx_sda/gpio16 5 gpio15_in r - the pin status of sst/tsi_clk/ibx_clk/gpio15. 4 gpio14_in r - the pin status of cirwb#/tsi_dat/ibx_sda/gpio14. 3 gpio13_in r - the pin status of cirtx/tsi_clk/ibx_clk/gpio13. 2 gpio12_in r - the pin status of cir_led#gpio12/wdtrst# 1 gpio11_in r - the pin status of fanctl3/gpio11/irtx1. 0 gpio10_in r - the pin status of fanin3/gpio10/irrx1. gpio1 drive enable register ? index e3h bit name r/w default description 7 reserved - - reserved. 6 gpio16_drv_en r/w 0 0: gpio16 is open drain in output mode. 1: gpio16 is push pull in output mode. 5 gpio15_drv_en r/w 0 0: gpio15 is open drain in output mode. 1: gpio15 is push pull in output mode. 4 gpio14_drv_en r/w 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. 0 gpio10_drv_en r/w 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. gpio2 output enable register ? index d0h bit name r/w default description 7 gpio27_oe r/w 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 0 0: gpio26 is in input mode. 1: gpio25 is in output mode. 5 gpio25_oe r/w 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4-0 reserved - - reserved. gpio2 output data register ? index d1h bit name r/w default description 7 gpio27_val r/w 1 0: gpio27 outputs 0 when in output mode. 1: gpio27 outputs 1 when in output mode. 6 gpio26_val r/w 1 0: gpio26 outputs 0 when in output mode. 1: gpio26 outputs 1 when in output mode.
sep, 2011 v0.21p -95- F71889A 5 gpio25_val r/w 1 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4-0 reserved - - reserved. gpio2 pin status register ? index d2h bit name r/w default description 7 gpio27_in r - the pin status of sus_warn#/gpio27. 6 gpio26_in r - the pin status of slp_sus#/gpio26. 5 gpio25_in r - the pin st atus of cirrx#/gpio25. 4-0 reserved - - reserved. gpio2 drive enable register ? index d3h bit name r/w default description 7 gpio27_drv_en r/w 0 0: gpio27 is open drain in output mode. 1: gpio27 is push pull in output mode. 6 gpio26_drv_en r/w 0 0: gpio26 is open drain in output mode. 1: gpio26 is push pull in output mode. 5 gpio25_drv_en r/w 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4-0 reserved - - reserved. gpio3 output enable register ? index c0h bit name r/w default description 7 gpio37_oe r/w 0 0: gpio37 is in input mode. 1: gpio37 is in output mode. 6 gpio36_oe r/w 0 0: gpio36 is in input mode. 1: gpio35 is in output mode. 5 gpio35_oe r/w 0 0: gpio35 is in input mode. 1: gpio35 is in output mode. 4 gpio34_oe r/w 0 0: gpio34 is in input mode. 1: gpio34 is in output mode. 3 gpio33_oe r/w 0 0: gpio33 is in input mode. 1: gpio33 is in output mode. 2 gpio32_oe r/w 0 0: gpio32 is in input mode. 1: gpio32 is in output mode. 1 gpio31_oe r/w 0 0: gpio31 is in input mode. 1: gpio31 is in output mode. 0 gpio30_oe r/w 0 0: gpio30 is in input mode. 1: gpio30 is in output mode. gpio3 output data register ? index c1h bit name r/w default description 7 gpio37_val r/w 1 0: gpio37 outputs 0 when in output mode. 1: gpio37 outputs 1 when in output mode.
sep, 2011 v0.21p -96- F71889A 6 gpio36_val r/w 1 0: gpio36 outputs 0 when in output mode. 1: gpio36 outputs 1 when in output mode. 5 gpio35_val r/w 1 0: gpio35 outputs 0 when in output mode. 1: gpio35 outputs 1 when in output mode. 4 gpio34_val r/w 1 0: gpio34 outputs 0 when in output mode. 1: gpio34 outputs 1 when in output mode. 3 gpio33_val r/w 1 0: gpio33 outputs 0 when in output mode. 1: gpio33 outputs 1 when in output mode. 2 gpio32_val r/w 1 0: gpio32 outputs 0 when in output mode. 1: gpio32 outputs 1 when in output mode. 1 gpio31_val r/w 1 0: gpio31 outputs 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w 1 0: gpio30 outputs 0 when in output mode. 1: gpio30 outputs 1 when in output mode. gpio3 pin status register ? index c2h bit name r/w default description 7 gpio37_in r - the pin stat us of sin2/sege/gpio37. 6 gpio36_in r - the pin stat us of sout2/segb/gpio36/ ovp_strap. 5 gpio35_in r - the pin stat us of dsr2#/l#/gpio35. 4 gpio34_in r - the pin status of rts2#/segc/gpio34/pwm_dc. 3 gpio33_in r - the pin stat us of dtr2#/segd/gpio33. 2 gpio32_in r - the pin stat us of cts2#/sega/gpio32. 1 gpio31_in r - the pin st atus of ri2#/gpio31. 0 gpio30_in r - the pin status of dcd2#/gpio30. gpio3 drive enable register ? index c3h bit name r/w default description 7 gpio37_drv_en r/w 0 0: gpio37 is open drain in output mode. 1: gpio37 is push pull in output mode. 6 gpio36_drv_en r/w 0 0: gpio36 is open drain in output mode. 1: gpio36 is push pull in output mode. 5 gpio35_drv_en r/w 0 0: gpio35 is open drain in output mode. 1: gpio35 is push pull in output mode. 4 gpio34_drv_en r/w 0 0: gpio34 is open drain in output mode. 1: gpio34 is push pull in output mode. 3 gpio33_drv_en r/w 0 0: gpio33 is open drain in output mode. 1: gpio33 is push pull in output mode. 2 gpio32_drv_en r/w 0 0: gpio32 is open drain in output mode. 1: gpio32 is push pull in output mode. 1 gpio31_drv_en r/w 0 0: gpio31 is open drain in output mode. 1: gpio31 is push pull in output mode. 0 gpio30_drv_en r/w 0 0: gpio30 is open drain in output mode. 1: gpio30 is push pull in output mode.
sep, 2011 v0.21p -97- F71889A gpio4 output enable register ? index b0h bit name r/w default description 7 gpio47_oe r/w 0 0: gpio47 is in input mode. 1: gpio47 is in output mode. 6 gpio46_oe r/w 0 0: gpio46 is in input mode. 1: gpio45 is in output mode. 5 gpio45_oe r/w 0 0: gpio45 is in input mode. 1: gpio45 is in output mode. 4 gpio44_oe r/w 0 0: gpio44 is in input mode. 1: gpio44 is in output mode. 3 gpio43_oe r/w 0 0: gpio43 is in input mode. 1: gpio43 is in output mode. 2 gpio42_oe r/w 0 0: gpio42 is in input mode. 1: gpio42 is in output mode. 1 gpio41_oe r/w 0 0: gpio41 is in input mode. 1: gpio41 is in output mode. 0 gpio40_oe r/w 0 0: gpio40 is in input mode. 1: gpio40 is in output mode. gpio4 output data register ? index b1h bit name r/w default description 7 gpio47_val r/w 1 0: gpio47 outputs 0 when in output mode. 1: gpio47 outputs tri-state when in output mode. 6 gpio46_val r/w 1 0: gpio46 outputs 0 when in output mode. 1: gpio46 outputs tri-state when in output mode. 5 gpio45_val r/w 1 0: gpio45 outputs 0 when in output mode. 1: gpio45 outputs tri-state when in output mode. 4 gpio44_val r/w 1 0: gpio44 outputs 0 when in output mode. 1: gpio44 outputs tri-state when in output mode. 3 gpio43_val r/w 1 0: gpio43 outputs 0 when in output mode. 1: gpio43 outputs tri-state when in output mode. 2 gpio42_val r/w 1 0: gpio42 outputs 0 when in output mode. 1: gpio42 outputs tri-state when in output mode. 1 gpio41_val r/w 1 0: gpio41 outputs 0 when in output mode. 1: gpio41 outputs tri-state when in output mode. 0 gpio40_val r/w 1 0: gpio40 outputs 0 when in output mode. 1: gpio40 outputs tri-state when in output mode. gpio4 pin status register ? index b2h bit name r/w default description 7 gpio47_in r - the pin status of gpio47. 6 gpio46_in r - the pin status of gpio46. 5 gpio45_in r - the pin status of gpio45. 4 gpio44_in r - the pin status of gpio44.
sep, 2011 v0.21p -98- F71889A 3 gpio43_in r - the pin status of gpio43. 2 gpio42_in r - the pin status of gpio42. 1 gpio41_in r - the pin status of gpio41. 0 gpio40_in r - the pin status of gpio40. gpio5 output enable register ? index a0h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_oe r/w 0 0: gpio54 is in input mode. 1: gpio54 is in output mode. 3 gpio53_oe r/w 0 0: gpio53 is in input mode. 1: gpio53 is in output mode. 2 gpio52_oe r/w 0 0: gpio52 is in input mode. 1: gpio52 is in output mode. 1 gpio51_oe r/w 0 0: gpio51 is in input mode. 1: gpio51 is in output mode. 0 gpio50_oe r/w 0 0: gpio50 is in input mode. 1: gpio50 is in output mode. gpio5 output data register ? index a1h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_val r/w 1 0: gpio54 outputs 0 when in output mode. 1: gpio54 outputs tri-state when in output mode. 3 gpio53_val r/w 1 0: gpio53 outputs 0 when in output mode. 1: gpio53 outputs tri-state when in output mode. 2 gpio52_val r/w 1 0: gpio52 outputs 0 when in output mode. 1: gpio52 outputs tri-state when in output mode. 1 gpio51_val r/w 1 0: gpio51 outputs 0 when in output mode. 1: gpio51 outputs tri-state when in output mode. 0 gpio50_val r/w 1 0: gpio50 outputs 0 when in output mode. 1: gpio50 outputs tri-state when in output mode. gpio5 pin status register ? index a2h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_in r - the pin status of gpio54. 3 gpio53_in r - the pin status of gpio53. 2 gpio52_in r - the pin status of gpio52. 1 gpio51_in r - the pin status of gpio51. 0 gpio50_in r - the pin status of gpio50.
sep, 2011 v0.21p -99- F71889A gpio5 pme enable register ? index a4h bit name r/w default description 7-5 reserved - - reserved 4 gpio54_pme_en r/w 0 when gpio54_event_sts is 1 and gpio54_pme_en is set to 1, a gpio pme event will be generated. 3 gpio53_pme_en r/w 0 when gpio53_event_sts is 1 and gpio53_pme_en is set to 1, a gpio pme event will be generated. 2 gpio52_pme_en r/w 0 when gpio52_event_sts is 1 and gpio52_pme_en is set to 1, a gpio pme event will be generated. 1 gpio51_pme_en r/w 0 when gpio51_event_sts is 1 and gpio51_pme_en is set to 1, a gpio pme event will be generated. 0 gpio50_pme_en r/w 0 when gpio50_event_sts is 1 and gpio50_pme_en is set to 1, a gpio pme event will be generated. gpio5 input detection select register ? index a5h bit name r/w default description 7-5 reserved - - reserved 4 gpio54_det_sel r/w 0 when gpio54 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 3 gpio53_det_sel r/w 0 when gpio53 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 2 gpio52_det_sel r/w 0 when gpio52 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 1 gpio51_det_sel r/w 0 when gpio51 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 0 gpio50_det_sel r/w 0 when gpio50 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge gpio5 event status register ? index a6h bit name r/w default description 7-5 reserved - - reserved 4 gpio54_ event_sts r/w - when gpio54 is in input mode and a gpio54 input is detected according to cra5 [4], this bit will be set to 1. write a 1 to this bit will clear it to 0. 3 gpio53_ event_sts r/w - when gpio53 is in input mode and a gpio53 input is detected according to cra5 [3], this bit will be set to 1. write a 1 to this bit will clear it to 0.
sep, 2011 v0.21p -100- F71889A 2 gpio52_ event_sts r/w - when gpio52 is in input mode and a gpio52 input is detected according to crb5 [2], this bit will be set to 1. write a 1 to this bit will clear it to 0. 1 gpio51_ event_sts r/w - when gpio51 is in input mode and a gpio51 input is detected according to crb5 [1], this bit will be set to 1. write a 1 to this bit will clear it to 0. 0 gpio50_ event_sts r/w - when gpio50 is in input mode and a gpio50 input is detected according to crb5 [0], this bit will be set to 1. write a 1 to this bit will clear it to 0. gpio52 kbc emulation make code register ? index abh bit name r/w default description 7-0 gp52_make_code r/w 0 this is the make code for gpio52 kbc emulation. the break code will be gp52_make_code + 0x80. gpio51 kbc emulation make code register ? index ach bit name r/w default description 7-0 gp51_make_code r/w 0 this is the make code for gpio51 kbc emulation. the break code will be gp51_make_code + 0x80. gpio50 kbc emulation make code register ? index adh bit name r/w default description 7-0 gp50_make_code r/w 0 this is the make code for gpio50 kbc emulation. the break code will be gp50_make_code + 0x80. gpio5 kbc emulation prefix code register ? index aeh bit name r/w default description 7-0 gp_pre_code r/w e0h this is the prefix code for gpio5 kbc emulation. when pre_code_en is set, prefix code followed by make/break code is sent when the event occurs. gpio5 kbc emulation control register ? index afh bit name r/w default description 7 gp_kbc_en r/w 0 set ?1? to enable gpio5 kbc emulation. 6 pre_code_en r/w 0 0: disable prefix code. make/break code is sent when the event occurs. 1: enable prefix code. prefix code follow ed by make/break code is sent when the event occurs. 5 gp52_brk_ste r/wc 0 this bit is set when gpio52 is released (rising edge) and auto cleared by host reading 0x60 port. it could be clear by writing ?1?. 4 gp52_make_ste r/wc 0 this bit is set when gpio52 is pressed (falling edge) and auto cleared by host reading 0x60 port. it could be clear by writing ?1?. the status will continue to set when still pressing the gp io52. the delay time is 0.5 ~ 1 sec and repeated time is 50ms. 5 gp51_brk_ste r/wc 0 this bit is set when gpio51 is released (rising edge) and auto cleared by host reading 0x60 port. it could be clear by writing ?1?. 5 gp51_make_ste r/wc 0 this bit is set when gpio51 is pressed (falling edge) and auto cleared by host reading 0x60 port. it could be clear by writing ?1?. the status will continue to set when still pressing the gp io51. the delay time is 0.5 ~ 1 sec and repeated time is 50ms. 5 gp50_brk_ste r/wc 0 this bit is set when gpio50 is released (rising edge) and auto cleared by host reading 0x60 port. it could be clear by writing ?1?.
sep, 2011 v0.21p -101- F71889A 0 gp50_make_ste r/wc 0 this bit is set when gpio50 is pressed (falling edge) and auto cleared by host reading 0x60 port. it could be clear by writing ?1?. the status will continue to set when still pressing the gpio50 i. the delay time is 0.5 ~ 1 sec and repeated time is 50ms. gpio6 output enable register ? index 90h bit name r/w default description 7 gpio67_oe r/w 0 0: gpio67 is in input mode. 1: gpio67 is in output mode. 6 gpio66_oe r/w 0 0: gpio66 is in input mode. 1: gpio65 is in output mode. 5 gpio65_oe r/w 0 0: gpio65 is in input mode. 1: gpio65 is in output mode. 4 gpio64_oe r/w 0 0: gpio64 is in input mode. 1: gpio64 is in output mode. 3 gpio63_oe r/w 0 0: gpio63 is in input mode. 1: gpio63 is in output mode. 2 gpio62_oe r/w 0 0: gpio62 is in input mode. 1: gpio62 is in output mode. 1 gpio61_oe r/w 0 0: gpio61 is in input mode. 1: gpio61 is in output mode. 0 gpio60_oe r/w 0 0: gpio60 is in input mode. 1: gpio60 is in output mode. gpio6 output data register ? index 91h bit name r/w default description 7 gpio67_val r/w 1 0: gpio67 outputs 0 when in output mode. 1: gpio67 outputs 1 when in output mode. 6 gpio66_val r/w 1 0: gpio66 outputs 0 when in output mode. 1: gpio66 outputs 1 when in output mode. 5 gpio65_val r/w 1 0: gpio65 outputs 0 when in output mode. 1: gpio65 outputs 1 when in output mode. 4 gpio64_val r/w 1 0: gpio64 outputs 0 when in output mode. 1: gpio64 outputs 1 when in output mode. 3 gpio63_val r/w 1 0: gpio63 outputs 0 when in output mode. 1: gpio63 outputs 1 when in output mode. 2 gpio62_val r/w 1 0: gpio62 outputs 0 when in output mode. 1: gpio62 outputs 1 when in output mode. 1 gpio61_val r/w 1 0: gpio61 outputs 0 when in output mode. 1: gpio61 outputs 1 when in output mode. 0 gpio60_val r/w 1 0: gpio60 outputs 0 when in output mode. 1: gpio60 outputs 1 when in output mode.
sep, 2011 v0.21p -102- F71889A gpio6 pin status register ? index 92h bit name r/w default description 7 gpio67_in r - the pin status of stb#/gpio67. 6 gpio66_in r - the pin status of afd /gpio66. 5 gpio65_in r - the pin status of err#/ gpio65. 4 gpio64_in r - the pin status of init#/ gpio64. 3 gpio63_in r - the pin status of ack#/gpio63. 2 gpio62_in r - the pin status of busy/gpio62. 1 gpio61_in r - the pin status of pe/gpio61. 0 gpio60_in r - the pin status of slct/gpio60. gpio6 drive enable register ? index 93h bit name r/w default description 7 gpio67_drv_en r/w 0 0: gpio67 is open drain in output mode. 1: gpio67 is push pull in output mode. 6 gpio66_drv_en r/w 0 0: gpio66 is open drain in output mode. 1: gpio66 is push pull in output mode. 5 gpio65_drv_en r/w 0 0: gpio65 is open drain in output mode. 1: gpio65 is push pull in output mode. 4 gpio64_drv_en r/w 0 0: gpio64 is open drain in output mode. 1: gpio64 is push pull in output mode. 3 gpio63_drv_en r/w 0 0: gpio63 is open drain in output mode. 1: gpio63 is push pull in output mode. 2 gpio62_drv_en r/w 0 0: gpio62 is open drain in output mode. 1: gpio62 is push pull in output mode. 1 gpio61_drv_en r/w 0 0: gpio61 is open drain in output mode. 1: gpio61 is push pull in output mode. 0 gpio60_drv_en r/w 0 0: gpio60 is open drain in output mode. 1: gpio60 is push pull in output mode. gpio7 output enable register ? index 80h bit name r/w default description 7 gpio77_oe r/w 0 0: gpio77 is in input mode. 1: gpio77 is in output mode. 6 gpio76_oe r/w 0 0: gpio76 is in input mode. 1: gpio75 is in output mode. 5 gpio75_oe r/w 0 0: gpio75 is in input mode. 1: gpio75 is in output mode. 4 gpio74_oe r/w 0 0: gpio74 is in input mode. 1: gpio74 is in output mode. 3 gpio73_oe r/w 0 0: gpio73 is in input mode. 1: gpio73 is in output mode. 2 gpio72_oe r/w 0 0: gpio72 is in input mode. 1: gpio72 is in output mode.
sep, 2011 v0.21p -103- F71889A 1 gpio71_oe r/w 0 0: gpio71 is in input mode. 1: gpio71 is in output mode. 0 gpio70_oe r/w 0 0: gpio70 is in input mode. 1: gpio70 is in output mode. gpio7 output data register ? index 81h bit name r/w default description 7 gpio77_val r/w 1 0: gpio77 outputs 0 when in output mode. 1: gpio77 outputs 1 when in output mode. 6 gpio76_val r/w 1 0: gpio76 outputs 0 when in output mode. 1: gpio76 outputs 1 when in output mode. 5 gpio75_val r/w 1 0: gpio75 outputs 0 when in output mode. 1: gpio75 outputs 1 when in output mode. 4 gpio74_val r/w 1 0: gpio74 outputs 0 when in output mode. 1: gpio74 outputs 1 when in output mode. 3 gpio73_val r/w 1 0: gpio73 outputs 0 when in output mode. 1: gpio73 outputs 1 when in output mode. 2 gpio72_val r/w 1 0: gpio72 outputs 0 when in output mode. 1: gpio72 outputs 1 when in output mode. 1 gpio71_val r/w 1 0: gpio71 outputs 0 when in output mode. 1: gpio71 outputs 1 when in output mode. 0 gpio70_val r/w 1 0: gpio70 outputs 0 when in output mode. 1: gpio70 outputs 1 when in output mode. gpio7 pin status register ? index 82h bit name r/w default description 7 gpio77_in r - the pin status of pd7/gpio77. 6 gpio76_in r - the pin status of pd6/gpio76. 5 gpio75_in r - the pin status of pd5/ gpio75. 4 gpio74_in r - the pin status of pd4/gpio74. 3 gpio73_in r - the pin status of pd3/gpio73. 2 gpio72_in r - the pin status of pd2/gpio72. 1 gpio71_in r - the pin status of pd1/gpio71. 0 gpio70_in r - the pin status of pd0/gpio70. gpio7 drive enable register ? index 83h bit name r/w default description 7 gpio77_drv_en r/w 0 0: gpio77 is open drain in output mode. 1: gpio77 is push pull in output mode. 6 gpio76_drv_en r/w 0 0: gpio76 is open drain in output mode. 1: gpio76 is push pull in output mode. 5 gpio75_drv_en r/w 0 0: gpio75 is open drain in output mode. 1: gpio75 is push pull in output mode. 4 gpio74_drv_en r/w 0 0: gpio74 is open drain in output mode. 1: gpio74 is push pull in output mode.
sep, 2011 v0.21p -104- F71889A 3 gpio73_drv_en r/w 0 0: gpio73 is open drain in output mode. 1: gpio73 is push pull in output mode. 2 gpio72_drv_en r/w 0 0: gpio72 is open drain in output mode. 1: gpio72 is push pull in output mode. 1 gpio71_drv_en r/w 0 0: gpio71 is open drain in output mode. 1: gpio71 is push pull in output mode. 0 gpio70_drv_en r/w 0 0: gpio70 is open drain in output mode. 1: gpio70 is push pull in output mode. 8.8 watch dog timer registers (cr07) watchdog timer configuration register ? index f0h ( * cleared by slotocc_n and watch dog timeout) bit name r/w default description 7 wdout_en r/w 0 if this bit is set to 1 and watchdog timeout event occurs, wdtrst# output is enabled. 6-1 reserved - 0 reserved 0 wd_rst_en r/w 0 0: disable wdt. 1: enable wdt to reset the vid register marked with *. watchdog timer configuration register 1 ? index f5h bit name r/w default description 7 reserved r 0 reserved 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1:0 wd_pswidth r/w 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec watchdog timer configuration register 2 ? index f6h bit name r/w default description 7:0 wd_time r/w 0 time of watchdog timer wdt pme register ? index fah bit name r/w default description 7 wdt_pme r 0 0: no wdt pme occurred. 1: wdt pme occurred. the wdt pme is occurred one unit before wdt timeout. 6 wdt_pme_en r/w 0 0: disable wdt pme. 1: enable wdt pme. 5-1 reserved r 0 reserved 0 cpu_change r/w 0 this bit will be set at slotocc# rise edge. internal 1us de-bounce circuit is implemented. write ?1? to this bit will clear the status. *those register are reset by slotocc# falling edge (c pu change) or watchdog timer timeout (if enabled).
sep, 2011 v0.21p -105- F71889A 8.9 cir registers (cr08) configuration registers cir enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 cir_en r/w 0 0: disable cir 1: enable cir base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of cir base address. base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of cir base address. cirirq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selcirirq r/w 0h select the irq channel for cir interrupt. device register cir status register ? index 00h bit name r/w default description 7 cir_irq_en r/w 0 cir irq function enable 6-4 reserved r 0 reserved 3 tx_finish r/w 0 cir transmittion finish status. write 1 clear. 2 tx_underrun r/w 0 cir transmitttion underrun status. write 1 clear. 1 rx_timeout r/w 0 cir receiver timeout status. write 1 clear. 0 rx_receive r/w 0 cir receiver receives data status. write 1 clear. cir rx data register ? index 01h bit name r/w default description 7-0 rx_data r - cir received data is read from here.
sep, 2011 v0.21p -106- F71889A cir tx control register ? index 02h bit name r/w default description 7 tx_start r/w 0 set 1 to start cir tx transmittion and will be auto cleared if transmittion is finished. 6 tx_end r/w 0 set 1 to indicate that all tx data has been written to cir tx fifo. 5-0 reserved - - reserved cir tx data register ? index 03h bit name r/w default description 7-0 tx_data r/w - the transmittion data should be written to tx_data. cir control register ? index 04h bit name r/w default description 7-0 cir_cmd r/w 0 host writes command to cir. 8.10 pme, acpi and erp registers (cr0a) pme device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. pme event enable 1 register ? index f0h bit name r/w default description 7 reserved - - reserved 6 mo_pme_en r/w 0 mouse pme event enable. 0: disable mouse pme event. 1: enable mouse pme event. 5 kb_pme_en r/w 0 keyboard pme event enable. 0: disable keyboard pme event. 1: enable keyboard pme event. 4 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. 3 prt_pme_en r/w 0 parallel port pme event enable. 0: disable parallel port pme event. 1: enable parallel port pme event. 2 ur2_pme_en r/w 0 uart 2 pme event enable. 0: disable uart 2 pme event. 1: enable uart 2 pme event.
sep, 2011 v0.21p -107- F71889A 1 ur1_pme_en r/w 0 uart 1 pme event enable. 0: disable uart 1 pme event. 1: enable uart 1 pme event. 0 reserved r/w 0 reserved. pme event status 1 register ? index f1h bit name r/w default description 7 reserved - - reserved 6 mo_pme_st r/w - mouse pme event status. 0: mouse has no pme event. 1: mouse has a pme event to assert. wr ite 1 to clear to be ready for next pme event. 5 kb_pme_st r/w - keyboard pme event status. 0: keyboard has no pme event. 1: keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 4 hm_pme_st r/w - hardware monitors pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 3 prt_pme_st r/w - parallel port pme event status. 0: parallel port has no pme event. 1: parallel port has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ur2_pme_st r/w - uart 2 pme event status. 0: uart 2 has no pme event. 1: uart 2 has a pme event to assert. write 1 to clear to be ready for next pme event. 1 ur1_pme_st r/w - uart 1 pme event status. 0: uart 1 has no pme event. 1: uart 1 has a pme event to assert. write 1 to clear to be ready for next pme event. 0 reserved r/w - reserved pme event enable 2 register ? index f2h bit name r/w default description 7-5 reserved - - reserved 4 cir_pme_en r/w 0 cir pme event enable. 0: disable cir pme event. 1: enable cir pme event. 3 reserved - - reserved 2 ri2_pme_en r/w 0 ri2# pme event enable. 0: disable ri2# pme event. 1: enable ri2# pme event.
sep, 2011 v0.21p -108- F71889A 1 ri1_pme_en r/w 0 ri1# pme event enable. 0: disable ri2# pme event. 1: enable ri2# pme event. 0 gp_pme_en r/w 0 gpio pme event enable. 0: disable gpio pme event. 1: enable gpio pme event. pme event status 2 register ? index f3h bit name r/w default description 7-5 reserved - - reserved 4 cir_pme_st r/w - cir pme event status. 0: cir has no pme event. 1: cir has a pme event to assert. write 1 to clear to be ready for next pme event. 3 erp_pme_st r/w - erp pme event status. 0: erp has no pme event. 1: erp has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ri2_pme_st r/w - ri2# pme event status. 0: ri2# has no pme event. 1: ri2# has a pme event to assert. writ e 1 to clear to be ready for next pme event. 1 ri1_pme_st r/w - ri1# pme event status. 0: ri1# has no pme event. 1: ri1# has a pme event to assert. writ e 1 to clear to be ready for next pme event. 0 gp_pme_st r/w - gpio pme event status (operate only under s0 stage). 0: gpio has no pme event. 1: gpio has a pme event to assert. writ e 1 to clear to be ready for next pme event. acpi control register 1 ? index f4h bit name r/w default description 7 reserved r/w 0 reserved 6 en_cirwakeup r/w 0 set one to enable cir wakeup event asserted via psout#.
sep, 2011 v0.21p -109- F71889A 5 dual_gate_s5_o n r/w 1 0: dual_gate_n tri-state in s5 state. 1: dual_gate_n output low in s5 state. 4 en_kbwakeup r/w 0 set one to enable key board wakeup event asserted via pwsout#. 3 en_mowakeup r/w 0 set one to enable mouse wakeup event asserted via pwsout#. 2-1 pwrctrl r/w 11 the acpi control the pson_n to always on or always off or keep last state 00 : keep last state 10 : always on 01 : always on without psout# 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it acpi control register 2 ? index f5h bit name r/w default description 7 reserved r/w 0 dummy for future use. 6-5 pwrok_delay r/w 0 the additional pwrok delay. 00: no delay 01: 100ms. 10: 200ms 11: 400ms. 4-3 vdd_delay r/w 00 the pwrok delay timing from v dd3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 2 vindb_en r/w 1 enable the pc irstin_n and atxpwgd de-bounce. 1 pcirst_db_en r/w 0 enab le the lreset_n de-bounce. 0 reserved r/w 0 dummy register. acpi control register 3 ? index f6h bit name r/w default description 7 s3_sel r/w 0 select the kbc s3 state. 0: enter s3 state when internal vdd3vok signal de-asserted. 1: enter s3 state when s3# is low or the ts3 register is set to 1. 6 reserved - - reserved. 5 wdt_rst_en r/w 0 0: disable wdt time out reset signal 1: enable wdt time out reset signal output form pwrok. 4 pson_del_en r/w 0 0: pson# is the inverted of s3# signal. 1: pson# will sink low only if the time af ter the last turn-off elapse at least 4 seconds. 3 vref_s3_rst_en r/w 0 0: the vref output value programmed by user will keep in s3/s5 state. 1: the vref output value will be rese t to default (64h) when enter s3/s5 state. 2 pcirst3_gate r/w 1 write ?0? to this bit will force pcirst3# to sink low. 1 pcirst2_gate r/w 1 write ?0? to this bit will force pcirst2# to sink low. 0 pcirst1_gate r/w 1 write ?0? to this bit will force pcirst1# to sink low.
sep, 2011 v0.21p -110- F71889A acpi control register 4 ? index f7h bit name r/w default description 7 usben_ds5_st r/w 0 usben deep output value in deep s5 state. (powered by vbat) 6 usben_s5_st r/w 0 usben deep output value in s5 state. (powered by vbat) 5 usben_ds3_st r/w 0 usben deep output value in deep s3 state. 4 usben_s3_st r/w 1 usben deep output value in s3 state. 3-2 reserved r/w - reserved 1-0 vcc_gate_delay r/w 00 vccgate# will be low when s3# is high, vcc3v is power on and vcc5v is power on. this register define the delay time from the condition is ready: 00: 10ms 01: 50ms 10: 100ms 11: 200ms led additional mode select ? index fah (powered by vbat) bit name r/w default description 7 reserved r/w - reserved 6 led_vsb_s5_add r/w 0 refer to led_vsb_s5_mode. 5 led_vsb_s3_add r/w 0 refer to led_vsb_s3_mode. 4 led_vsb_s0_add r/w 0 refer to led_vsb_s0_mode. 3 reserved r/w - reserved 2 led_vcc_s5_add r/w 0 refer to led_vcc_s5_mode. 1 led_vcc_s3_add r/w 0 refer to led_vcc_s3_mode. 0 led_vcc_s0_add r/w 0 refer to led_vcc_s0_mode. intel dsw delay select register ? index fch bit name r/w default description 7-5 reserved r/w - reserved 4 dual_gate_dsw_en r/w 0 when this bit is set ?1?. dualgate will be inverted of sus_warn#. 3-0 dsw_delay r/w 7h this is the delay time for sus_ack# and sus_warn#. time unit is 0.5s. ri de-bounce select register ? index feh bit name r/w default description 7-5 reserved - - reserved 4 ir_vdd_s3 r/w 0 set ?1? to emulate s3 state for cir. 3-2 reserved - - reserved
sep, 2011 v0.21p -111- F71889A 1-0 ri_db_sel r/w 0 select ri de-bounce time. 00: reserved. 01: 200us. 10: 2ms. 11: 20ms. erp enable register ? index e0h bit name r/w default description 7 erp_en r/w 1 0 : disable erp function 1: enable erp function 6 s3_back r/w 0 when this bit is set. it indi cates the system is back from s3 state. 5 reserved - - reserved 4 event1_en r/w 0 usben/event_in1# function select. 0: the pin function is usben. 1: the pin function is event_in1#. 3 event1_pme_en r/w 0 event1 pme# event enable. 0: disable event1 pme# event. 1: enable event1 pme# event, when ring1 falling edge detect 2 event1_psout_e n r/w 0 event1 psout# event enable. 0: disable event1 psou#t event. 1: enable event1 psout# event, when ring2 falling edge detect 1 event0_pme_en r/w 0 event0 pm#e event enable. 0: disable event0 pme# event. 1: enable event0 pme# event, when ring1 falling edge detect 0 event0_psout_e n r/w 0 event0 psout# event enable. 0: disable event0 psout# event. 1: enable event0 psout# event, when ring1 falling edge detect erp control register ? index e1h bit name r/w default description 7-6 boot_mode r/w 11 write these two bits to select boot mode for always off/ always on/ keep last state. 00:default always off 11:support always on and keep last state 10:reserved 01:reserved 5 s3_ ctrl_1_dis r/w 0 if clear to ?0? ctrl_1 will output low when s3 state. else if set to ?1? ctrl_1 will output high when s3 state. 4 s3 _ctrl_0_dis r/w 0 if clear to ?0? ctrl_0 will output low when s3 state. else if set to ?1? ctrl_0 will output high when s3 state. 3 s5 _ctrl_1_dis r/w 1 if clear to ?0? ctrl_1 will output low when s5 state. else if set to ?1? ctrl_1 will output high when s5 state. 2 s5 _ctrl_0_dis r/w 1 if clear to ?0? ctrl_0 will output low when s5 state. else if set to ?1? ctrl_0 will output high when s5 state.
sep, 2011 v0.21p -112- F71889A 1 ac_ ctrl_1_dis r/w 0 if clear to ?0? ctrl_1 will output low w hen after ac lost. else if set to ?1? ctrl_1 will output high when after ac lost. 0 ac_ ctrl_0_dis r/w 0 if clear to ?0? ctrl_0 will output low w hen after ac lost. else if set to ?1? ctrl_0 will output high when after ac lost. erp control register ? index e2h bit name r/w default description 7 ac_lost r/wc - ?1? indicates an ac lost occurs. write ?1? to clear. 6 reserved - - reserved. 5 vsb_ctrl_en[1] r/w 1?b0 0: disable erp_ctrl1# assert rsmrst# low 1: enable erp_ctrl 1# assert rsmrst# low 4 vsb_ctrl_en[0] r/w 1?b0 0: disable erp_ctrl0# assert rsmrst# low 1: enable erp_ctrl0# assert rsmrst# low 3-1 reserved - - reserved 0 rsmrst_det_3v_ n r/w 0 device detects vsb5v power ok (4.4v) and vsb3v_in become high, and after 60ms de-bounce time rsmrst will become high. but when user set this bit to 1. rsmrst will not check vsb3v_in pin status. erp psin deb-register ? index e3h bit name r/w default description 7-0 ps_deb_time r/w 0x13 ps_in# pin input de-bounce time: the unit of this register is 1ms, default is 20ms. erp rsmrst deb-register ? index e4h bit name r/w default description 7-0 rsmrst_deb_time r/w 0x09 rsmrst# internal de-bounce time: the unit of this register is 1ms, default is 10ms. erp psout deb-register ? index e5h bit name r/w default description 7-0 ps_out_pulse_w r/w 0xc7 ps_out_out output pulse widt h: the unit of this register is 1ms , default is 200ms low pulse erp pson deb-register ? index e6h bit name r/w default description 7-0 ps_on_deb_time r/w 0x09 pson_in pin input de-bounce time: the unit of this register is 1ms, default is 10ms. erp s5 deb-register ? index e7h bit name r/w default description 7-0 s5_deb_time r/w 0x63 s5# pin input de-bounce time the unit of this register is 64ms, default is 6.4s.
sep, 2011 v0.21p -113- F71889A erp wakeup event enable register ? index e8h bit name r/w default description 7 ri2_wakeup_en r/w 0 enable ri2# pme# event to wakeup. 6 cir_wakeup_en r/w 0 enable cir pme# event to wakeup. 5 ri1_wakeup_en r/w 0 enable ri1# pme# event to wakeup. 4 event_wakeup_en r/w 1 enable event_in# event to wakeup. 3 reserved r/w 0 reserved 2 tmout_wakeup_en r/w 0 enable erp watchdog timer timeout event to wakeup. see index edh and eeh. 1 mo_wakeup_en r/w 0 enable mouse pme# event to wakeup. 0 kb_wakeup_en r/w 0 enable keyboard pme# event to wakeup. erp deep s3 delay register ? index e9h bit name r/w default description 7-0 s3_del_time r/w 0xff s3 to deep s3 delay time. the unit of this register is 64ms, default is 16.32s. erp control register 2 ? index ech bit name r/w default description 7-6 erp_mode r/w 00 erp mode select. 00: fintek g3`. 01: fintek g3` + intel dsw. 10: reserved. 11: intel dsw. 5 dpwrok_ctrl_en r/w 0 set ?1? to enble dpwrok reset by erp_ctrl1#. 4 vsb_ctrl_en[2] r/w 1?b0 0: disable erp_ctrl2# assert rsmrst# low 1: enable erp_ctrl 2# assert rsmrst# low 3 revered - - reserved. 2 s3 _ctrl_2_dis r/w 0 if clear to ?0? ctrl_2 will output low in deep s3 state. else if set to ?1? ctrl_2 will output high in deep s3 state. 1 s5 _ctrl_2_dis r/w 1 if clear to ?0? ctrl_2 will output low in deep s5 state. else if set to ?1? ctrl_2 will output high in deep s5 state. 0 ac_ ctrl_2_dis r/w 0 if clear to ?0? ctrl_2 will output low w hen after ac lost. else if set to ?1? ctrl_2 will output high when after ac lost. erp watchdog control register ? index edh bit name r/w default description 7-5 revered - - reserved. 4 wd_tmout r/wc 0 erp watchdog timer timeout status. write 1 to clear. 3-2 revered - - reserved.
sep, 2011 v0.21p -114- F71889A 1 wd_unit r/w 0 0: unit of wd_time is 1 sec. 1: unit of wd_time is 1 minute. 0 wd_en r/w 0 enable erp watchdog timer. erp watchdog time register ? index eeh bit name r/w default description 7-0 wd_time r/w 0 erp watchdog timer count time register. start to count down when wd_en is set. when reaching 0, wd_en will auto clear and wd_tmout is set. a wakeup event will assert if enabled 8.11 vref control registers (cr0b) vref3 output value ? index f0h bit name r/w default description 7-0 vref3_h r/w 8?h64 the bit8-1 of vref3 output value. vref2 output value ? index f1h bit name r/w default description 7-0 vref2_h r/w 8?h64 the bit8-1 of vref2 output value. vref1 output value ? index f2h bit name r/w default description 7-0 vref1_h r/w 8?h64 the bit8-1 of vref1 output value. wdt reset enable ? index ffh bit name r/w default description 7-1 reserved. - - reserved. 0 wd_rst_en r/w 0 0: disable the wdt reset function. 1: vref1~3 will be reset to default if wdt timeout occurs.
sep, 2011 v0.21p -115- F71889A 9 electrical characteristics absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to 70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device all acpi timing accuracy is 20%. dc characteristics (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) (note) parameter conditions min typ max unit temperature error, remote diode 60 o c < t d < 100 o c, vcc = 3.0v to 3.6v -40 o c sep, 2011 v0.21p -116- F71889A output low current iol -18 ma vol = 0.4 v output high current ioh +18 ma voh = 2.4v input high leakage ilih +1 i/ood 12,5v -ttl level bi-directional pin, output pin with 12ma source-sink capability, and can programming to open-drain function, 5v tolerance. input low threshold voltage vt- 0.8 v vdd = 3.3 v input high threshold voltage vt+ 2.0 v vdd = 3.3 v output low current iol -12 -9 ma vol = 0.4 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 i/od 14t -ttl level bi-directional pin, open-dra in output with14 ma sink capability. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol -14 ma vol = 0.4 v i/o 16t - ttl level bi-directional pin, output pin with 16ma source-sink capability. input low threshold voltage vt- 0.6 v vdd = 3.3 v input high threshold voltage vt+ 0.9 v vdd = 3.3 v output high current ioh +16 ma voh = 2.4v input high leakage ilih +1 in st - ttl level input pin with schmitt trigger input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 in t , 5v - ttl level input pin with 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 in st , 5v - ttl level input pin with schmitt trigger, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 in st , lv - ttl level input pin with schmitt trigger, low level. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 od 12 -open-drain output with12 ma sink capability. output low current iol -12 ma vol = 0.4v od 12 , 5 v -open-drain output with12 ma sink capability, 5v tolerance. output low current iol -12 ma vol = 0.4v od 16 , u10 , 5 v -open-drain output with 16 ma sink capability, pull-up 10k ohms, 5v tolerance. output low current iol -16 ma vol = 0.4v o 8 , u47 , 5v - output pin with 8 ma source-sink capability, pull-up 47k ohms, 5v tolerance. output high current ioh +6 +8 ma voh = 2.4v o 12 - output pin with 12 ma source-sink capability. output high current ioh +9 +12 ma voh = 2.4v o 16 - output pin with 16 ma source-sink capability.
sep, 2011 v0.21p -117- F71889A output high current ioh +16 ma voh = 2.4v o 18 - output pin with 18 ma source-sink capability. output high current ioh +18 ma voh = 2.4v o 24 - output pin with 24 ma source-sink capability. output high current ioh +24 ma voh = 2.4v o 14 - output pin with 14 ma source-sink capability. output high current ioh +14 ma voh = 2.4v o 30 - output pin with 30 ma source-sink capability. output high current ioh +26 +30 ma voh = 2.4v i/o s1, d8,st, lv - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.) with schmitt trigger. output with 8ma drive and 1ma sink capability. input low voltage vil 0.6 v input high voltage vih 0.9 v output high current ioh +8 ma voh = 1.0v input low leakage ilil -1 i/o d8,st, lv - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.) with schmitt trigger. output with 8ma drive input low voltage vil 0.6 v input high voltage vih 0.9 v output high current ioh +8 ma voh = 1.0v input high leakage ilih +1 ilil -1 i/od 12st,lv - low level bi-directional pin with schmitt tr igger. open-drain output with 12ma sink capability. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol -12 ma voh = 0.4v input high leakage ilih +1 ilil -1 i/ood 12st,lv - low level bi-directional pin with schmitt trigger, can select to od or out by register, with 12 ma source-sink capability. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol -12 ma voh = 0.4v input high leakage ilih +1 i/od 12st,5v -ttl level bi-directional pin with schmitt tri gger, open-drain output with12 ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol +12 ma vol = 0.4v input high leakage ilih +1 i/od 16st,5v -ttl level bi-directional pin with schmitt trigger, open-drain output with 16 ma sink capability, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol +16 ma vol = 0.4v input high leakage ilih +1
sep, 2011 v0.21p -118- F71889A 10 ordering information 11 top marking specification the version identification is shown as the bold red three characters. please refer to below table for detail: part number package type production flow F71889Ad 128-lqfp green package commercial, 0 c to +70 c 1 st line: fintek logo 2 nd line: device name where the last alphabet always means package code ? F71889A d 3 rd line: assembly plant code (x) + assembled year code (x) + week code (xx) + fintek internal code (xx) + ic version (x) where a means version, b means version b, ? 4 th line: wafer fab code (xxxx?xx) : pin 1 identifier F71889Ad xxxxxx x xxxxxx.x fintek
sep, 2011 v0.21p -119- F71889A 12 package dimensions 128 lqfp (14*14) feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
sep, 2011 v0.21p 120 F71889A 13 application circuit vbat 1 2 c3 0.1u dualgate 1 2 c2 0.1u r1 0 (gnd close to ic) slct vref1 pson# vbat vref_en pe copen# vin6 busy vref3 pwrok vin5 vin4 s5# d- vin2 rsmrst# atxpg_in s3# vref2 d3+ vin3 vcore mdata mclk kdata kclk d2+ pme# d1+ vref vccgate vsb3v pwsin# pwsout# 3va 1 2 c81 0.1u kbrst# vcc3v pciclk clk_24/48m clk_24/48m lad2 lad2 lad3 pciclk lad3 atxpg_in d11 diode/nc atxpg_in vcc3v vbat d13 diode sin2 d14 diode dtr2# vbat vsb3v pcirst# ldrq# lad0 dtr2# rts2# sout2 serirq lad1 lframe# tp12 fanctl1 fanin1 pcirst# sout2 fanin2 lframe# serirq lad1 lad0 fanctl2 dsr2# ldrq# fanctl3 fanin3 rts2# tp1 tp13 decouple atx power supply noise. tp2 r11 560 rts1# sout2 sout1 dtr1# r11 off: ovp warning mode on: ovp force mode r12 off: pwm on: dac r13 off: fan 60% on: fan 100% r14 off: 80 port enable on: 80 port disable r15 off: config 4e on :config 2e r13 560 r14 560 r12 560 rts2# power trip r r15 560 tp3 slp_sus# sus_warn# cirrx# ovt# pcirst1# led_vsb led_vcc tp4 dpwrok slotocc# sus_ack# beep erp_ctrl2# 5va ovt# usben/event_in1# r16 10 event_in0# ga20 peci sst erp_ctrl1# cirwb# cirtx erp_ctrl0# cir_led# pcirst2# pcirst3# tp5 tp6 pwrok rsmrst# vsb3v vsb3v rsmrst# and pwok pull up r9 4.7k r10 4.7k tp7 r178 0/nc tit le size document number rev date: sheet of F71889A feature integration technology inc. b 16 wednesday , april 13, 2011 tp8 sin1 pd0 slin# pd1 rts1# dtr1# tp9 sout1 dcd2# dcd1# init# ri1# ri2# cts1# pd3 pd2 pd5 pd4 pd6 err# cts2# pd7 dsr1# ack# afd# dtr1# sout1 rts1# stb# tp10 tp11 r18 2m vbat slotocc# slotocc# slotocc# slotocc#_cpu slotocc# slotocc# slot_occ# vcc 1 dtr2#/segd/gpio33 2 rts2#/segc/pwm_dc 3 dsr2#/l# 4 sout2/segb/gpio36/ovp_strap 5 sin2/sege/gpio37 6 gpio40/cir_led# 7 gpio41 8 gpio42 9 gpio43 10 gpio44 11 gpio45 12 gpio46 13 gpio47 14 gpio50(vol up) 15 gpio51(vol down) 16 gpio52(mute) 17 gpio53(pwm up) 18 gpio54(pwm down) 19 gnd 20 fanin1 21 fanctl1 22 fanin2 23 fanctl2 24 fanin3/gpio10/irtx1 25 fanctl3/gpio11/irrx1 26 lreset# 27 ldrq# 28 serirq 29 lfram# 30 lad0 31 lad1 32 lad2 33 lad3 34 vcc 35 pciclk 36 clkin 37 kbrst# 38 pcirst3# 64 pcirst2# 63 pcirst1# 62 ovt# 61 susc#/gpio06/beep/alert# 60 gpio05/led_vcc 59 gpio04/led_vsb 58 slotocc#/gpio03 57 dpwrok/gpio02 56 sus_ack#/gpio01 55 erp_ctrl2#/gpio00 54 sus_warn#/gpio27 53 slp_sus#/gpio26 52 cirrx#/gpio25 51 gnd 50 vsb5v 49 erp_ctrl1# 48 erp_ctrl0# 47 usben/event_in1# 46 event_in0# 45 peci/tsi_dat/ibx_sda/gpio16 44 sst/tsi_clk/ibx_clk/gpio15 43 cirwb#/tsi_dat/ibx_sda/gpio14 42 cirtx/tsi_clk/ibx_clk/gpio13 41 gpio12/wdtrst#/cir_led# 40 ga20 39 busy /gpio62 102 pe/gpio61 101 slct/gpio60 100 3vsb 99 vcore(vin1) 98 vin2 97 vin3 96 vin4 95 vin5 94 vin6 93 vref 92 d1+(cpu) 91 d2+ 90 d3+(system) 89 agnd(d-) 88 vref1 87 vref2 86 vref3 85 copen# 83 vbat 82 rsmrst# 81 pwok 80 ps_on# 79 s3# 78 psout# 77 psin# 76 pme# 75 atxpg_in 74 s5# 73 dualgate 72 vccgate 71 gnd 70 mclk 69 mdata 68 kclk 67 kdata 66 i_vsb3v 65 ack#/gpio63 103 slin#/coretp 104 init#/gpio64 105 err#/gpio65 106 afd#/gpio66 107 stb#/gpio67 108 pd0/gpio70 109 pd1/gpio71 110 pd2/gpio72 111 pd3/gpio73 112 pd4/gpio74 113 pd5/gpio75 114 pd6/gpio76 115 pd7/gpio77 116 gnd 117 dcd1# 118 ri1# 119 cts1# 120 dtr1#/fan60_100 121 rts1#/80port_trap 122 dsr1# 123 sout1/conf ig4e_2e 124 sin1 125 dcd2#/segg/gpio30 126 ri2#/segf/gpio31 127 cts2#/sega/gpio32 128 vref_en 84 F71889A u1 1 2 c72 0.1u vref3 1 2 c59 0.1u vref2 1 2 c60 0.1u vref1 1 2 c61 0.1u (place the capcitor close to ic) vcc3v 1 2 c77 0.1u 1 2 c1 0.1u vsb3v vcc3v 1 2 c5 0.1u
sep, 2011 v0.21p 121 F71889A if you do not use the kbc, please pull-up these pin to vsb5v. vcc5v r20 4.7k c25 100p r21 4.7k f1 fuse c26 0.1u l1 fb l3 fb c24 100p ps2 mouse interface 1 2 3 4 5 6 js1 m-din_6-r r22 4.7k l2 fb 1 2 3 4 5 6 js2 m-d i n _6-r c27 100p c29 0.1u l4 fb c28 100p f2 fuse ps2 keyboard interface r23 4.7k 1 2 3 j3 con3 vsb5v mc lk md at kclk kdat tit le size document number rev date: sheet of uart_ps2_ir 0.1 feature intergration technology inc custom 26 friday , april 16, 2010 dcd1# rin1 ri1# cts1# dsr1# sout2 dcd2# +12v cts2# ri2# -12v rts2# dsr2# vcc5v rin2 rtsn2 dtrn2 ctsn2 dsrn2 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u3 gnd sinn2 ctsn2 soutn2 dcdn2 soutn2 sin1 sinn2 dsrn2 dcdn2 rtsn2 rin2 dtrn2 5 9 4 8 3 7 2 6 1 p2 uart db9 uart 2 port interface dtr2# sin2 ri2# dcd2# dsr2# cts2# sin2 r145 4.7k if you do not use the uart port 2, please pull-up these pin to vcc3v. r146 4.7k r147 4.7k r148 4.7k vcc3v r149 4.7k uart 1 port interface if you do not use the uart port 1, please pull-up these pin to vcc3v. r140 4.7k chipset_ri1# r160 8.2k r161 2.2k r162 4.7k vsb3v q17 npn c58 1000p d10 1n4148 rin1 sin1 dcd1# cts1# ri1# dtr1# dsr1# sout1 rts1# 4.7k rin1 r142 4.7k dtrn1 gnd dsrn1 ctsn1 sinn1 rtsn1 dcdn1 soutn1 ctsn1 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u2 dcdn1 dtrn1 dsrn1 sinn1 5 9 4 8 3 7 2 6 1 p1 uart db9 rtsn1 soutn1 +12v vcc5v -12v r143 4.7k wake up on ring for serial port circuit. r144 4.7k vcc3v vcc5v/3v 1 2 3 4 5 jp1 header 5 ir interface fanctl3 fanin3 c23 0.1u
sep, 2011 v0.21p 122 F71889A +12v r30 10k 1 2 3 jp3 con3 r33 10k r32 3.6k d3 1n4148 3 2 1 8 4 + - u4a lm358 fanctl2 r31 27k r27 4.7k c32 47u nds0605/sot c33 0.1u r28 100 fanin1 1 2 3 4 jp2 4 header r25 4.7k r29 10k r26 27k +12v d2 1n4148 c31 0.1u fanctl1 fanin2 +12v r43 10k 1 2 3 jp5 con3 r45 10k r44 3.6k d5 1n4148 5 6 7 8 4 + - u4b lm358 r42 27k r40 4.7k c36 47u q3 nds0605/sot c37 0.1u fanin3 r101 4.7k +12v c35 0.1u r41 10k r38 27k r102 4.7k 2 1 3 q2 pnp r35 4.7k r34 4.7k r37 4.7k +12v + c34 47u 1 2 3 jp4 header 3 vcc5v r24 10k r39 330 g d s q4 mosfet n 2n7002 d4 1n4148 tit le size document number rev date: sheet of fan control 0.1 feature integration technology inc. b 36 friday , nov ember 06, 2009 r103 4.7k r53 10k 1 2 3 jp7 con3 r57 10k r56 3.6k d6 1n4148 3 2 1 8 4 + - u5a lm358 r51 27k r50 4.7k c39 47u q5 nds0605/sot c41 0.1u fanctl1 fanin2 c40 0.1u r55 10k r52 27k fanctl2 2 1 3 q6 pnp r48 4.7k r46 4.7k r49 4.7k +12v + c38 47u 1 2 3 jp6 header 3 r54 330 pwm fan1 speed control g d s q7 mosfet n 2n7002 d7 1n4148 fanctl3 fanin3 pwm fan3 speed control dc fan control with op 1 r36 4.7k vcc3v fanctl3 dc fan control with op 2 fanin1 r47 4.7k vcc3v (four pin fan control) pwm fan2 speed control fan control for pwm or dc + c30 47u dc fan control with op 3
sep, 2011 v0.21p 123 F71889A d8 led d9 led r81 4.7k vcc3v r125 4.7k r126 4.7k r127 4.7k q13 2n1069 vsb5v vsb5v q14 mosf et n q15 mosfet p c55 100u ~ 1000u +12v vcc5v 5v_dual vccgate dualgate c53 100u ~ 1000u ovt# ovt# pull-up r65 2k vref d1+ r69 10k 1% t rt1 thermistor 10k 1% (for system) q8 pnp 3906 for system d1+ from cpu d2+ vref q9 pnp 3906 r71 10k 1% for system t rt2 thermistor 10k 1% d3+ (for system) d3+ c45 3300p diode sensing circuit d- thermistor sensing circuit d- d1+ d2+ d+ d- c43 3300p d2+ c42 3300p temperature sensing diode sensing circuit d- d3+ vref r72 10k 1% t rt3 thermistor 10k 1% (for system) thermistor sensing circuit r75 4.7k c47 100p c48 100p c49 100p c50 100p c51 100p c52 100p vin4 r62 20k r63 4.7k r64 20k r61 10k r59 1k r60 100k -12v vcore +5vsb voltage sensing. the best voltage input level is about 1v. +5v vin2 vcore vin3 vin5 +12v vin6 r70 10k vcc1.5v r67 20k vsb5v vref c54 100u ~ 1000u tit le size document number rev date: sheet of hardware monitor feature integration technology inc. b 46 thursday , april 15, 2010 power control r58 2m vbat c44 1000p copen# case open circuit 1 2 sw1 led_vsb sus_led vsb5v vsb3v q11 npn r74 330 r73 4.7k led p_led led_vcc vsb3v vsb5v q10 npn r66 330 r68 4.7k
sep, 2011 v0.21p 124 F71889A 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 j2 db25 1 2 3 4 5 6 7 8 rn3 2.7k-8p4r busy 1 2 3 4 5 6 7 8 rn1 2.7k-8p4r r19 2.7k vcc5v (female) slct 1 2 d1 1n5819 c20 180p pe busy c6 180p c14 180p c7 180p c15 180p c8 180p c16 180p c9 180p c17 180p c10 180p c18 180p c11 180p c19 180p c12 180p c21 180p c13 180p c22 180p slct pe err# ack# vcc3v slct pe ack# busy r155 4.7k err# r156 4.7k r157 4.7k r158 4.7k r159 4.7k if you do not use the prarllel port , please pull-up these pin to vcc3v. tit le size document number rev date: sheet of printer port feature integration technology inc. b 56 friday , april 16, 2010 for lekage to power parallel port interface 1 2 3 4 5 6 7 8 rn5 33-8p4r 1 2 3 4 5 6 7 8 rn6 33-8p4r 1 2 3 4 5 6 7 8 rn7 33-8p4r 1 2 3 4 5 6 7 8 rn2 2.7k-8p4r 1 2 3 4 5 6 7 8 rn4 2.7k-8p4r pd0 slin# init# pd1 pd3 pd2 pd5 pd4 pd6 err# ack# pd7 afd# stb#
sep, 2011 v0.21p 125 F71889A rts2# sout2 sin2 dcd2# dtr2# ri2# cts2# dsr2# h# 80 port (output by com2 interface) h# vcc3v r82 4.7k dsr2# g d s q16 mosfet n nc 2 segg 1 sega 3 segf 4 h# 10 segc 8 segb 9 sege 7 l# 5 segd 6 u8 dual digit display r138 100 r139 100 r96 300 r97 300 r98 100k r99 100k vddio peci sst peci sst sid sic peci_client sst_host amdtsi sst peci (avoid pre-bios floating) (avoid pre-bios floating) client r109 300 intel ibex r123 300 peci vcc3v smlink[1] sst title size document number rev date: sheet of amdtsi/sst/peci/80port feature integration technology inc. b 66 friday , april 16, 2010
sep, 2011 v0.21p 126 F71889A 5va 5vusb r181 1k c78 10u c79 10u q23 mosfet p usben/event_in1# c80 1u r185 10k v3a r179 10k dpwrok dsw pull up dsw slp_sus# r180 r sus_warn# r182 0 r183 0 slp_sus# sus_ack# r184 sus_ack# sus_warn# r186 r sus_warn# sus_warn#(chipset) dpwrok r188 r dpwrok select sus_warn# to chipset or 5v_dual 5v_dual sus_ack# v3a r190 10k tit le size document number rev date: sheet of erp_control feature integration technology inc. b 11 monday , may 31, 2010 pson# pwsout# r124 1k pme# 5va r163 10k r164 10k r165 10k 5vsb c63 10u c64 10u q12 mosfet p c65 1u erp_ctrl0# 5va 5va r166 1k 5vusb c66 10u c67 10u q18 mosfet p erp_ctrl1# c68 1u erp control vsb r167 10k r168 10k vsb3v usben/event_in1# pwsin# r169 10k erp acpi pull up r170 10k r171 10k event_in0# 5vusb 5va r172 1k c69 10u c70 10u q19 mosfet p erp_ctrl2# c71 1u r173 10k
sep, 2011 v0.21p 127 F71889A tit le size document number rev date: sheet of cir feature integration technology inc. a 11 friday , april 16, 2010 choose power and capacitance by ir receiver vcc3v 2 1 3 q20 npn3904 r150 330 r151 100 c73 10nf c74 0.1u r152 1.8k r153 330 wide band ir receiver r154 12k vsb3v q21 2n7002 1 2 q22 ltr-301 r174 0r vsb5v r175 0r out 1 vcc 2 gnd 3 case 4 u9 gp1ud260y k c75 0.1u long rang ir receiver c76 10u 1 2 3 j5 tx1 j ac k vsb3v r176100 tx port r177 330 ir led 1 2 d12 led cirtx cirled# cirwb# cirrx#
sep, 2011 v0.21p 128 F71889A tit le size document number rev date: sheet of acpi block feature integration technology inc. b 11 monday , may 31, 2010 cpt pch sw2 wake event (g3')erp_ctrl1# (dsw)erp_ctrl0# 5va g3'_ctl dsw_ctl ps_in# event_in# erp block ps_on# ps_on# i_3vsb vbat 3vsb rsmrst# vcc_gate pme# pwrok 5vdual sus_warn# s5# s3# ri cir waek up event kb/ms rtc wake waek up event acpi block acpi block ldo3v atxpg_in d15 g3'_ctl atx_pg dsw_ctl 5vcc 5vsb_atx atx power supply F71889A ps_out# 3va 3vsb 5vsb sus_ack# sus_warn# 5vsb rsmrst# slp_sus# pwrbtn# slp_s4# slp_s3# pme# dpwrok dsw block slp_sus# sus_ack# sus_warn# dpwrok dsw block 3vldo en pwrok gpio27 erp_ctrl2# erp_ctrl2

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